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ADDR10 Datasheet(PDF) 64 Page - List of Unclassifed Manufacturers

Part # ADDR10
Description  Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins
PDF  68 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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ADDR10 Datasheet(HTML) 64 Page - List of Unclassifed Manufacturers

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Ex te r n a l DM A t i mi ng
60
NS 93 60 Da ta shee t
03 /2 00 6
Memory-to-memory external DMA
Notes:
1
A null period sometimes occurs between memory cycles.
2
The memory signals are data[31:0], addr[27:0], BE[3:0], CS/RAS[4:0], CAS[3:0], RW, OE*. WE*,
and PORTA2/AMUX. The timing of these signals depends on how the memory is configured
(Sync SRAM, Async SRAM, FP DRAM, or SDRAM).
T1
TW
T2
Note-1
T1
TW
T2
75
75
75
75
72
72
72
72
71
70
71
70
BCLK
Mem signals (Note-2)
R/W
DREQ*
DACK*
DONE* (output)



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