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ADDR10 Datasheet(PDF) 40 Page - List of Unclassifed Manufacturers

Part # ADDR10
Description  Figure 1 shows the NS7520 modules. Dashed lines indicate shared pins
PDF  68 Pages
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Manufacturer  ETC2 [List of Unclassifed Manufacturers]
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ADDR10 Datasheet(HTML) 40 Page - List of Unclassifed Manufacturers

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SRAM timing
36
NS 75 20 Da ta shee t
03 /2 00 6
SRAM OE read
OE* controlled read (wait = 2)
Notes:
1
At least one null period occurs between memory transfers. More null periods can occur if the
next transfer is DMA. Thirteen clock pulses are required for DMA context switching.
2
Port size determines which byte enable signals are active:
–
8-bit port = BE3*
–
16-bit port = BE[3:0]
–
32-bit port = BE[3:0]
3
The TW cycles are present when the WAIT field is set to 2 or more.
4
The TA* and TEA*/LAST signals are for reference only.
T1
TW
T2
Note-1
T1
12
18
18
28
28
27
27
36
36
6
31
31
30
30
11
10
15
14
Note-2
BCLK
TA* (Note-4)
TEA*/LAST (Note-4)
TA* (input)
A[27:0]
BE[3:0]*
CS[4:0]*
read D[31:0]
Async OE*
CS0OE*
RW*



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