MB9BF412RPMC-G-JNE2 datasheet(39/112 Pages) CYPRESS

39 / 112 page

Document Number: 002-05615 Rev. *D

Page

39 of 112

MB9B410R Series

Module

Pin name

Function

Pin No

LQFP-

100

FBGA-

112

LQFP-

120

QFP-

100

Clock

Main clock (oscillation) input pin

X0A

Sub clock (oscillation) input pin

Main clock (oscillation) I/O pin

L10

X1A

Sub clock (oscillation) I/O pin

CROUT_0

Built-in high-speed

CR-osc clock output port

C10

CROUT_1

107

Analog

Power

AVCC

A/D converter analog power pin

H11

AVRH

A/D converter analog reference voltage

input pin

F11

Analog

GND

AVSS

A/D converter GND pin

G11

C pin

Power stabilization capacity pin

Note:

− While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to all

requirements of that standard. This device may contain a 32-bit device ID that is the same as the 32-bit device ID in other

devices with different functionality. The TAP pins may also be configurable for purposes other than access to the TAP controller.

MB9BF412RPMC-G-JNE2 Datasheet(PDF) 39 Page - Cypress Semiconductor

MB9BF412RPMC-G-JNE2 Datasheet(HTML) 39 Page - Cypress Semiconductor

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