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MB9BF412RPMC-G-JNE2 Datasheet(PDF) 72 Page - Cypress Semiconductor |
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MB9BF412RPMC-G-JNE2 Datasheet(HTML) 72 Page - Cypress Semiconductor |
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72 / 112 page  Document Number: 002-05615 Rev. *D Page 72 of 112 MB9B410R Series Separate Bus Access Asynchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Min Max MOEX Min pulse width tOEW MOEX VCC ≥ 4.5 V MCLK×n-3 - ns VCC < 4.5 V MCSX ↓ → Address output delay time tCSL – AV MCSX[7:0] MAD[24:0] VCC ≥ 4.5 V - 9 +9 ns VCC < 4.5 V - 12 +12 MOEX ↑ → Address hold time tOEH - AX MOEX MAD[24:0] VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MCSX ↓ → MOEX ↓ delay time tCSL - OEL MOEX MCSX[7:0] VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 MOEX ↑ → MCSX ↑ time tOEH - CSH VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MCSX ↓ → MDQM ↓ delay time tCSL - RDQML MCSX MDQM[1:0] VCC ≥ 4.5 V MCLK×m-9 MCLK×m+9 ns VCC < 4.5 V MCLK×m-12 MCLK×m+12 Data set up → MOEX ↑ time tDS - OE MOEX MADATA[15:0] VCC ≥ 4.5 V 20 - ns VCC < 4.5 V 38 - MOEX ↑ → Data hold time tDH - OE MOEX MADATA[15:0] VCC ≥ 4.5 V 0 - ns VCC < 4.5 V MWEX Min pulse width tWEW MWEX VCC ≥ 4.5 V MCLK×n-3 - ns VCC < 4.5 V MWEX ↑ → Address output delay time tWEH - AX MWEX MAD[24:0] VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MCSX ↓ → MWEX ↓ delay time tCSL - WEL MWEX MCSX[7:0] VCC ≥ 4.5 V MCLK×n-9 MCLK×n+9 ns VCC < 4.5 V MCLK×n-12 MCLK×n+12 MWEX ↑ → MCSX ↑ delay time tWEH - CSH VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 MCSX ↓→ MDQM ↓ delay time tCSL-WDQML MCSX MDQM[1:0] VCC ≥ 4.5 V MCLK×n-9 MCLK×n+9 ns VCC < 4.5 V MCLK×n-12 MCLK×n+12 MCSX ↓→ Data output time tCSL - DV MCSX MADATA[15:0] VCC ≥ 4.5 V MCLK- 9 MCLK +9 ns VCC < 4.5 V MCLK- 12 MCLK +12 MWEX ↑ → Data hold time tWEH - DX MWEX MADATA[15:0] VCC ≥ 4.5 V 0 MCLK×m+9 ns VCC < 4.5 V MCLK×m+12 Note: − When the external load capacitance = 30 pF. (m = 0 to 15, n = 1 to 16) |
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