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MB9BF412RPMC-G-JNE2 Datasheet(PDF) 69 Page - Cypress Semiconductor |
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MB9BF412RPMC-G-JNE2 Datasheet(HTML) 69 Page - Cypress Semiconductor |
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69 / 112 page  Document Number: 002-05615 Rev. *D Page 69 of 112 MB9B410R Series 12.4.4 Operating Conditions of Main PLL (In the case of using main clock for input of PLL) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 4 - 16 MHz PLL multiple rate - 13 - 75 multiple PLL macro oscillation clock frequency fPLLO 200 - 300 MHz Main PLL clock frequency*2 fCLKPLL - - 144 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM3 Family PERIPHERAL MANUAL. 12.4.5 Operating Conditions of Main PLL (In the case of using high-speed internal CR) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Value Unit Remarks Min Typ Max PLL oscillation stabilization wait time*1 (LOCK UP time) tLOCK 100 - - μs PLL input clock frequency fPLLI 3.8 4 4.2 MHz PLL multiple rate - 50 - 71 multiple PLL macro oscillation clock frequency fPLLO 190 - 300 MHz Main PLL clock frequency*2 fCLKPLL - - 144 MHz *1: Time from when the PLL starts operating until the oscillation stabilizes. *2: For more information about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM3 Family PERIPHERAL MANUAL. When setting PLL multiple rate, please take the accuracy of the built-in high-speed CR clock into account and prevent the master clock from exceeding the maximum frequency. K divider PLL input clock Main PLL PLL macro oscillation clock M divider Main PLL clock (CLKPLL) N divider Main PLL connection High-speed CR clock (CLKHC) Main clock (CLKMO) |
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