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MB9BF412RPMC-G-JNE2 Datasheet(PDF) 83 Page - Cypress Semiconductor |
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MB9BF412RPMC-G-JNE2 Datasheet(HTML) 83 Page - Cypress Semiconductor |
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83 / 112 page  Document Number: 002-05615 Rev. *D Page 83 of 112 MB9B410R Series CSIO (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Baud rate - - - - 8 - 8 Mbps Serial clock cycle time tSCYC SCKx Master mode 4tCYCP - 4tCYCP - ns SCK ↑ → SOT delay time tSHOVI SCKx SOTx - 30 +30 - 20 + 20 ns SIN → SCK ↓ setup time tIVSLI SCKx SINx 50 - 30 - ns SCK ↓ → SIN hold time tSLIXI SCKx SINx 0 - 0 - ns Serial clock L pulse width tSLSH SCKx Slave mode 2tCYCP - 10 - 2tCYCP - 10 - ns Serial clock H pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK ↑ → SOT delay time tSHOVE SCKx SOTx - 50 - 30 ns SIN → SCK ↓ setup time tIVSLE SCKx SINx 10 - 10 - ns SCK ↓ → SIN hold time tSLIXE SCKx SINx 20 - 20 - ns SCK fall time tF SCKx - 5 - 5 ns SCK rise time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which Multi-function Serial is connected to, see 8 Block Diagram in this data sheet. − These characteristics only guarantee the same relocate port number. For example, the combination of SCKx_0 and SOTx_1 is not guaranteed. − When the external load capacitance = 30 pF. |
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