MB9BF412RPMC-G-JNE2 datasheet(67/112 Pages) CYPRESS

67 / 112 page

Document Number: 002-05615 Rev. *D

Page

67 of 112

MB9B410R Series

12.4

AC Characteristics

12.4.1

Main Clock Input Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)

Parameter

Symbol

name

Conditions

Value

Unit

Remarks

Min

Max

Input frequency

fCH

VCC ≥ 4.5 V

MHz

When crystal oscillator is

connected

VCC < 4.5 V

VCC ≥ 4.5 V

MHz

When using external

clock

VCC < 4.5 V

Input clock cycle

tCYLH

VCC ≥ 4.5 V

20.83

250

When using external

clock

VCC < 4.5 V

250

Input clock pulse

width

PWH/tCYLH

PWL/tCYLH

When using external

clock

Input clock rise

time and fall time

tCF,

tCR

When using external

clock

Internal operating

clock*1 frequency

fCM

144

MHz

Master clock

fCC

144

MHz

Base clock (HCLK/FCLK)

fCP0

MHz

APB0 bus clock*2

fCP1

MHz

APB1 bus clock*2

fCP2

MHz

APB2 bus clock*2

Internal operating

clock*1 cycle time

tCYCC

6.94

Base clock (HCLK/FCLK)

tCYCP0

13.8

APB0 bus clock*2

tCYCP1

13.8

APB1 bus clock*2

tCYCP2

13.8

APB2 bus clock*2

*1: For more information about each internal operating clock, see CHAPTER 2-1: Clock in FM3 Family PERIPHERAL MANUAL.

*2: For about each APB bus which each peripheral is connected to, see 8 Block Diagram in this data sheet.

MB9BF412RPMC-G-JNE2 Datasheet(PDF) 67 Page - Cypress Semiconductor

MB9BF412RPMC-G-JNE2 Datasheet(HTML) 67 Page - Cypress Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL