MB9BF412RPMC-G-JNE2 datasheet(71/112 Pages) CYPRESS

71 / 112 page

Document Number: 002-05615 Rev. *D

Page

71 of 112

MB9B410R Series

12.4.8

External Bus Timing

External bus clock output characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)

Parameter

Symbol

Pin name

Conditions

Value

Unit

Min

Max

Output frequency

tCYCLE

MCLKOUT*1

VCC ≥ 4.5 V

50*2

MHz

VCC < 4.5 V

32*3

MHz

*1: External bus clock (MCLKOUT) is divided clock of HCLK.

For more information about setting of clock divider, see CHPATER 12: External Bus Interface in FM3 Family PERIPHERAL

MANUAL.

When external bus clock is not output, this characteristic does not give any effect on external bus operation.

*2: When AHB bus clock frequency is more than 100MHz, the divider setting for MCLKOUT must be more than 4.

*3: When AHB bus clock frequency is more than 64MHz, the divider setting for MCLKOUT must be more than 4.

External bus signal input/output Characteristics

(VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C)

Parameter

Symbol

Conditions

Value

Unit

Remarks

Signal input characteristics

VIH

0.8 × VCC

VIL

0.2 × VCC

Signal output characteristics

VOH

0.8 × VCC

VOL

0.2 × VCC

VIH

VIL

VIH

VOH

VOL

VOH

MCLKOUT

Input signal

Output signal

MB9BF412RPMC-G-JNE2 Datasheet(PDF) 71 Page - Cypress Semiconductor

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