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MB9BF412RPMC-G-JNE2 Datasheet(PDF) 92 Page - Cypress Semiconductor |
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MB9BF412RPMC-G-JNE2 Datasheet(HTML) 92 Page - Cypress Semiconductor |
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92 / 112 page  Document Number: 002-05615 Rev. *D Page 92 of 112 MB9B410R Series 12.4.13 I2C Timing (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Conditions Standard-mode Fast-mode Unit Remarks Min Max Min Max SCL clock frequency FSCL CL = 30 pF, R = (Vp/IOL)*1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCLclock L width tLOW 4.7 - 1.3 - μs SCLclock H width tHIGH 4.0 - 0.6 - μs (Repeated) START setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45*2 0 0.9*3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between STOP condition and START condition tBUF 4.7 - 1.3 - μs Noise filter tSP 8 MHz ≤ tCYCP ≤ 40 MHz 2 tCYCP*4 - 2 tCYCP*4 - ns *5 40 MHz < tCYCP ≤ 60 MHz 3 tCYCP*4 - 3 tCYCP*4 - ns *5 60 MHz < tCYCP ≤ 72 MHz 4 tCYCP*4 - 4 tCYCP*4 - ns *5 *1: R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2: The maximum tHDDAT must satisfy that it doesn't extend at least L period (tLOW) of device's SCL signal. *3: Fast-mode I2C bus device can be used on Standard-mode I2C bus system as long as the device satisfies the requirement of tSUDAT ≥ 250 ns. *4: tCYCP is the APB bus clock cycle time. About the APB bus number that I2C is connected to, see 8 Block Diagram in this data sheet. To use Standard-mode, set the APB bus clock at 2 MHz or more. To use Fast-mode, set the APB bus clock at 8 MHz or more. *5: The number of the steps of the noise filter can be changed by register settings. Change the number of the noise filter steps according to APB2 bus clock frequency. SDA SCL |
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