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MB9BF412RPMC-G-JNE2 Datasheet(PDF) 76 Page - Cypress Semiconductor |
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MB9BF412RPMC-G-JNE2 Datasheet(HTML) 76 Page - Cypress Semiconductor |
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76 / 112 page ![]() Document Number: 002-05615 Rev. *D Page 76 of 112 MB9B410R Series Multiplexed Bus Access Synchronous SRAM Mode (VCC = 2.7V to 5.5V, VSS = 0V, TA = - 40°C to + 85°C) Parameter Symbol Pin name Conditions Value Unit Remarks Min Max MALE delay time tCHAL MCLK ALE VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 ns tCHAH VCC ≥ 4.5 V 1 9 ns VCC < 4.5 V 12 ns MCLK ↑ → Multiplexed Address delay time tCHMADV MCLK MADATA[15:0] VCC ≥ 4.5 V 1 tOD ns VCC < 4.5 V MCLK ↑ → Multiplexed Data output time tCHMADX VCC ≥ 4.5 V 1 tOD ns VCC < 4.5 V Note: − When the external load capacitance = 30 pF. MCLK MCSX[7:0] MALE MOEX MWEX MADATA[15:0] MAD [24:0] MDQM [1:0] |
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