ST20-GP1 datasheet(62/116 Pages) STMICROELECTRONICS

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ST20-GP1

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state as soon as the clocks are stable. All internal logic is static so no information is lost

during power down.

•

Power to most of the chip removed — only the real time clock supply (RTCVDD) power on.

10.2.1 Power-down mode

The ST20-GP1 enters power-down when:

•

the low power alarm is programmed and started, via conﬁguration registers, providing there

are no interrupts pending.

The ST20-GP1 exits power-down when:

•

an unmasked interrupt becomes pending.

•

the low power alarm counter reaches zero.

In power-down mode the processor and all peripherals are stopped, including the external memory

controller and optionally the PLL. Effectively the internal clock is stopped and functional operation

is stalled. On restart the clock is restarted and the chip resumes normal functional operation.

10.2.2 Low power mode

Low power mode can be achieved in one of two ways, as listed below.

•

Availability of direct clock input — this allows external control of clocking directly and thus

direct control of power consumption.

•

Internal global system clock may be stopped — in this case the external clock remains run-

ning. This mechanism allows the PLL to be kept running (if desired) so that wake up from

low power mode will be fast.

Wake-up from low power mode can be from: speciﬁc external pin activity (Interrupt pin); or the low

power timer alarm.

The low power timer and alarm are provided to control the duration for which the global clock

generation is stopped during low power mode. The timer and alarm registers can be set by the

device store instructions and read by the device load instructions.

Low power timer

The timer keeps track of real time, even when the internal clocks are stopped. The timer is a 64-bit

counter which runs off an external clock (LPClockIn). This clock rate must not be more than one

eighth of the system clock rate.

The real time clock is powered from a separate Vdd (RTCVDD) allowing it to be maintained at

minimal power consumption.

Low power alarm

There is also a 40-bit counter which can be used as a low power alarm or as a watchdog timer, this

is determined by the setting of the WdEnable register, see Table 10.10.

Alarm

A write to the LPAlarmStart register starts the low power alarm counter and the ST20-GP1 enters

low power mode. When the counter has counted down to zero, assuming no other valid wake-up

sources occur ﬁrst, the ST20-GP1 exits low power mode and the global clocks are turned back on.

Whilst the clocks are turned off the LowPowerStatus pin is high, otherwise it is low.

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