ST20-GP1 datasheet(56/116 Pages) STMICROELECTRONICS

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ST20-GP1

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in the following two cases:

•

The previous access was a read and the pending one is a write. The write access will not

start until the programmed number of BusReleaseTime cycles have elapsed.

•

The previous access was to a different bank to the pending access (bank switch). One

cycle is always inserted between accesses to different banks. Note that, if the ﬁrst condition

is also true, further cycles may be inserted to account for BusReleaseTime.

The ﬁrst case may be optimized slightly by making use of the DataDriveDelay conﬁguration

smaller, reducing the number of dead cycles, see Figure 9.4.

Figure 9.4 Use of DataDriveDelay parameter

Note, if DataDriveDelay is used, it must be used for all banks. If this rule is not adhered to, bus

contention may occur on bank switches. For example, consider case 2 in Figure 9.4 above. If the

BusReleaseTime coincides with the dead cycle inserted due to a bank switch, contention will

occur unless DataDriveDelay is programmed in the same way as if no bank switch had occurred.

9.4

MemWait

When enabled (see Table 9.4), MemWait is sampled at the midpoint of accesses which are

conﬁgured to be four cycles or greater. If the duration of the external access is not an even number

of cycles (i.e. the AccessDuration bit ﬁeld in the EMIConfigData register, see Table 9.4, is an odd

number), MemWait is sampled on the internal rising clock edge just after the midpoint of the

access.

Once a high has been sampled, the access is stalled. MemWait suspends the state of the EMI in

the cycle after it is sampled high. The state remains suspended until MemWait is sampled low. Any

strobe edges scheduled to occur in the cycle after MemWait is sampled will not occur. Strobe

edges scheduled to occur on the same edge as MemWait is sampled are not affected. Figure 9.5

and Figure 9.6 show the extension of the external memory cycle and the delaying of strobe

Read

Write

BusRelease

time

Case 1. DataDriveDelay set

to zero. All dead time taken up

by BusReleaseTime.

Read

Write

BusRelease

time

DataDriveDelay

Case 2. DataDriveDelay

used to absorb some

BusReleaseTime. Dead time

may be reduced.

Read data

Write data

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