ST20-GP1 datasheet(12/116 Pages) STMICROELECTRONICS

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ST20-GP1

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as doppler shift, crystal accuracy, etc.). The sum frequency (~8 MHz) is removed by low-pass

ﬁltering in the correlator.

This stage is common to all 12 channels.

Correlation against pseudo-random sequence

The GPS data is transmitted as a spread-spectrum signal (with a bandwidth of about 2 MHz). In

order to recover the data it is necessary to correlate against the same Pseudo-Random Noise

(PRN) signal that was used to transmit the data. The output of the correlator accumulator is

sampled at 264 KHz. The PRN sequences come from the PRN generator.

There is a correlator for the I and Q signals for each of the 12 channels. The output signal is now

narrowband.

Frequency conversion (B)

The second stage of frequency conversion mixes the data with the local oscillator signal generated

by the Numerically Controlled Oscillator (NCO). This signal is locked, under software control, to the

Space Vehicle (SV) frequency and phase to remove the errors and take the frequency and

bandwidth of the data down to 0 and

±50 Hz respectively. Filtering to 500 Hz is achieved in

hardware, to 50 Hz in software.

This stage is shared by time division multiplexing between all 12 channels. This is loss-free as the

stage supports 12 channels x 264 KHz, approximately 3 MHz, well within its 16 MHz clock rate.

Result integration

The ﬁnal stage sums the I and Q values for each channel over a user deﬁned period. In normal

operation, the sampling period is slightly less than the 1ms length of the PRN sequence. This

ensures that no data is lost, although it may mean that some data samples are seen twice — this is

handled (mainly) in software.

The sampling period can also be programmed to be much shorter (i.e. a higher cut-off frequency

for the ﬁlter) when the system is trying to ﬁnd new satellites (‘acquisition mode’).

There are two further stages of buffering for the accumulated 16-bit I and Q values for each

channel. These allow for the slightly different time domains involved1.

The results after hardware processing of the signal, using the parameters set in the DSP registers,

refer to Section 3.1, are delivered to the CPU via a DMA engine in packet format. The CPU should

perform an

in (input) instruction on the appropriate channel (see address map, Figure 7.1 on

page 47) in order to read a packet.

The format of the 62-byte packets is given in Figure 3.2. These represent a two byte header,

followed by the 16-bit I-values for 12 channels, then the 16-bit Q-values for 12 channels, then the 8-

bit timestamp values for the 12 channels. The I and Q values are sent least signiﬁcant byte ﬁrst.

The 2 byte header contains: a ‘sync’ byte with the value #1B, and a ‘sample rate’ byte which

contains the two SampleRate bits from the DSPControl register, see Table 3.1.

Packets are delivered at the rate selected by the DSPControl register, even if new data is not

available. In this case, the data value for the ﬁeld is set to #8000. This guarantees that synchronism

1. Data sampled in SV time, data transmitted to the CPU at ﬁxed intervals.

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