ST20-GP1 datasheet(30/116 Pages) STMICROELECTRONICS

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ST20-GP1

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workspace. The values of Iptr and Status to be used by the interrupt handler are loaded from this

workspace and starts executing the handler. The value of Wptr is then set to the bottom of this

save area.

When an interrupt occurs when the CPU was idle or running at low priority, the Status is saved.

This indicates that no valid process is running (

Null Status). The interrupted processes (low priority

process) state is stored in shadow registers. This state can be accessed via the

ldshadow (load

shadow registers) and

stshadow (store shadow registers) instructions. The interrupt handler is then

run at high priority.

When the interrupt routine has completed it must adjust Wptr to the value at the start of the

handler code and then execute the

iret (interrupt return) instruction. This restores the interrupted

state from the interrupt handler structure and signals to the interrupt controller that the interrupt has

completed. The processor will then continue from where it was before being interrupted.

5.3

Interrupt latency

The interrupt latency is dependent on the data being accessed and the position of the interrupt

handler and the interrupted process. This allows systems to be designed with the best trade-off use

of fast internal memory and interrupt latency.

5.4

Pre-emption and interrupt priority

Each interrupt channel has an implied priority ﬁxed by its place in the interrupt vector table. All

interrupts will cause scheduled processes of any priority to be suspended and the interrupt handler

started. Once an interrupt has been sent from the controller to the CPU the controller keeps a

record of the current executing interrupt priority. This is only cleared when the interrupt handler

executes a return from interrupt (

iret) instruction. Interrupts of a lower priority arriving will be

blocked by the interrupt controller until the interrupt priority has descended to such a level that the

routine will execute. An interrupt of a higher priority than the currently executing handler will be

passed to the CPU and cause the current handler to be suspended until the higher priority interrupt

is serviced.

In this way interrupts can be nested and a higher priority interrupt will always pre-empt a lower

priority one. Deep nesting and placing frequent interrupts at high priority can result in a system

where low priority interrupts are never serviced or the controller and CPU time are consumed in

nesting interrupt priorities and not executing the interrupt handlers.

5.5

Restrictions on interrupt handlers

There are various restrictions that must be placed on interrupt handlers to ensure that they interact

correctly with the rest of the process model implemented in the CPU.

Interrupt handlers must not deschedule.

Interrupt handlers must not execute communication instructions. However they may com-

municate with other processes through shared variables using the semaphore

signal to

synchronize.

Interrupt handlers must not perform block move instructions.

Interrupt handlers must not cause program traps. However they may be trapped by a

scheduler trap.

ST20-GP1 Datasheet(PDF) 30 Page - STMicroelectronics

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