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ADAU1373BCBZ-R7 Datasheet(PDF) 46 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 46 Page - Analog Devices |
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46 / 296 page  ADAU1373 Rev. 0 | Page 46 of 296 The PLL block consists of a digital PLL (DPLL), followed by an analog PLL (APLL) with multiplexer. This architecture allows flexibility in providing the clock to the ADAU1373. The DPLL can accept clock rates from 8 kHz to 8 MHz and outputs clock frequencies from 8 MHz to 27 MHz. The APLL can accept the clock output from the DPLL and provide further fine resolution to generate the clocks for internal blocks. If the input clock is greater than 8 MHz, the DPLL can be powered down to save power. In such a case, the external clock can be sent directly to the APLL. See Figure 93 for a diagram of clock distribution inside the ADAU1373. ÷N EXTERNAL CLOCK > 8MHz BCLKA BCLKB BCLKC MCLK1 LRCLKA LRCLKB LRCLKC GPIO1 GPIO2 GPIO3 GPIO4 MCLK2 DPLLB_REF_SEL DPLLB_NDIV 1....1024 IN 11 STEPS 8kHz TO 8MHz REG. 0x2F DPLLB_CTRL DPLLB DPLLB_CLK_OUT DPLLB LOCK INDICATOR ÷ X × (R + N/M) REG. 0x30 THROUGH REG. 0x35 PLLB CONTROL REGISTER EXTERNAL CLOCK (1024 × 48kHz)/(1024 × 44.1kHz) PLLB BYPASS PLL X = 1 TO 4 X = 1 DEFAULT R = 0 TO 15 M AND N 16-BIT BINARY NUMBER R = 2 DEFAULT M = 253 DEFAULT N = 0 DEFAULT APLLB CLOCK OUT FS_A_EXT ASRCA DSP DIGITAL AUDIO INTERFACE A ADC/ DMIC1_DOUT DECIMATOR DMIC2_DOUT ADC/ DMIC1 ADC 64 × fS DAC1 DAC2 DIGITAL MIC 2 INPUT DAC1_PB FDSP_CH0_DOUT MCLK2_OUT AIFCLK_A AIFCLK_B ÷ (P + 1) 5-BIT DIVIDER P = 0 TO 31 ÷1 TO 32 48kHz × 256 44.1kHz × 256 32kHz × 256 CLK2 OUT ×1024 ÷N EXTERNAL CLOCK > 8MHz BCLKA BCLKB BCLKC MCLK1 LRCLKA LRCLKB LRCLKC GPIO1 GPIO2 GPIO3 GPIO4 MCLK2 DPLLA_REF_SEL DPLLA_NDIV 1....1024 IN 11 STEPS 8kHz TO 8MHz REG. 0x28 DPLLA_CTRL DPLLA PLLB PLLA DPLLA_CLK_OUT DPLLA LOCK INDICATOR fINA ÷ X × (R + N/M) REG. 0x29 THROUGH REG. 0x2E PLLA CONTROL REGISTER EXTERNAL CLOCK (1024 × 48kHz)/(1024 × 44.1kHz) PLLA BYPASS CORE CLOCK ENABLE PLL X = 1 TO 4 X = 1 DEFAULT R = 0 TO 15 M AND N 16-BIT BINARY NUMBER R = 2 DEFAULT M = 253 DEFAULT N = 0 DEFAULT APLLA CLOCK OUT ANALOG PLLA ANALOG PLLB CLK1SDIV ADC CLK/ DAC1/2 CLK MCLK1 OUT AIFCLKB ÷ (J + 1) 3-BIT DIVIDER J = 0 TO 7 ÷1 TO 8 ÷ 2 ÷ (P + 1) 5-BIT DIVIDER P = 0 TO 31 ÷1 TO 32 INT CLK/ DEC CLK/ FDSP CLK ASRC CLK/ AIFCLKA MCLK1DIV CLK1_SOURCE_DIV (REG. 0x40) CLK1ODIV CLK1_OUTPUT_DIV (REG. 0x41) CLK2ODIV CLK2_OUTPUT_DIV (REG. 0x43) 128 × fs 128 × fs 256 × fs ÷ (K + 1) 3-BIT DIVIDER K = 0 TO 7 ÷1 TO 8 32kHz × 256 44.1kHz × 256 48kHz × 256 256 × fs CLK2SDIV ÷ (J + 1) 3-BIT DIVIDER J = 0 TO 7 ÷1 TO 8 MCLK2DIV CLK2_SOURCE_DIV (REG. 0x42) ÷ (K + 1) 3-BIT DIVIDER K = 0 TO 7 ÷1 TO 8 CLK1 OUT ×1024 DMIC_CLK DIGITAL MIC 1 INPUT ANALOG IN MIXER OUTPUT MIXER DECIMATOR DAC2_PB AIFA_REC AIFA_PB AIFB_REC AIFB_PB AIFC_REC AIFC_PB FDSP_CH0_DIN FDSP_CH1_DOUT FDSP_CH1_DIN FDSP_CH2_DOUT FDSP_CH2_DIN FDSP_CH3_DOUT FDSP_CH3_DIN FDSP_CH4_DOUT FDSP_CH4_DIN DEC_CLK (128 × fS) DEC_CLK (128 × fS) DEC_CLK (128 × fS) DEC_CLK (128 × fS) FDSP_CLK (128 × fS) ASRC_CLK (256 × fS) MIX/MUX BCLK_A DOUT_A DIN_A FS_A_INT BCLK_A DOUT_A DIN_A FS_DSP BCLK_DSP DOUT_DSP DIN_DSP FS_B_EXT ASRCB DIGITAL AUDIO INTERFACE B AIFCLK_A AIFCLK_B BCLK_B DOUT_B DIN_B FS_B_INT BCLK_B DOUT_B DIN_B FS_DSP BCLK_DSP DOUT_DSP DIN_DSP FS_C_EXT ASRCC DIGITAL AUDIO INTERFACE C AIFCLK A AIFCLK B (256 × fS) BCLK_C DOUT_C DIN_C FS_C_INT BCLK_C DOUT_C DIN_C FS_DSP BCLK_DSP DOUT_DSP DIN_DSP fINB Figure 93. Clock Distribution |
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