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ADAU1373BCBZ-R7 Datasheet(PDF) 73 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 73 Page - Analog Devices |
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73 / 296 page  ADAU1373 Rev. 0 | Page 73 of 296 REGISTER MAP SUMMARY (DEFAULT) Table 34 is the summary of the control registers for the ADAU1373 in default mode using an MDRC, which can be accessed using an I2C port. Register 0x80 to Register 0xBD are shared with the seven-band EQ block. Refer to the EQ register map (see Table 245) for using the EQ function. Register addresses are in hexadecimal format. Table 34. Register Summary Reg Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 00 INPUT_MODE [7:0] GAINMODE3 GAINMODE2 GAINMODE1 GAINMODE0 INMODE3 INMODE2 INMODE1 INMODE0 0x00 RW 01 AIN1L_CTRL [7:0] RESERVED AIN1LVOL 0x00 SRST 02 AIN1R_CTRL [7:0] RESERVED AIN1RVOL 0x00 SRST 03 AIN2L_CTRL [7:0] RESERVED AIN2LVOL 0x00 SRST 04 AIN2R_CTRL [7:0] RESERVED AIN2RVOL 0x00 SRST 05 AIN3L_CTRL [7:0] RESERVED AIN3LVOL 0x00 SRST 06 AIN3R_CTRL [7:0] RESERVED AIN3RVOL 0x00 SRST 07 AIN4L_CTRL [7:0] RESERVED AIN4LVOL 0x00 SRST 08 AIN4R_CTRL [7:0] RESERVED AIN4RVOL 0x00 SRST 09 LLINE1_OUT [7:0] RESERVED LLINE1 0x00 SRST 0A RLINE1_OUT [7:0] RESERVED RLINE1 0x00 SRST 0B LLINE2_OUT [7:0] RESERVED LLINE2 0x00 SRST 0C RLINE2_OUT [7:0] RESERVED RLINE2 0x00 SRST 0D LCD_OUT [7:0] RESERVED LCD 0x00 SRST 0E RCD_OUT [7:0] RESERVED RCD 0x00 SRST 0F LHP_OUT [7:0] RESERVED LHP 0x00 SRST 10 RHP_OUT [7:0] RESERVED RHP 0x00 SRST 11 ADC_GAIN [7:0] ADCRGAIN3 ADCRGAIN2 ADCRGAIN1 ADCRGAIN0 ADCLGAIN3 ADCLGAIN2 ADCLGAIN1 ADCLGAIN0 0x00 RW 12 LADC_MIXER [7:0] RESERVED ADCLMIX4 ADCLMIX3 ADCLMIX2 ADCLMIX1 ADCLMIX0 0x00 RW1C 13 RADC_MIXER [7:0] RESERVED ADCRMIX4 ADCRMIX3 ADCRMIX2 ADCRMIX1 ADCRMIX0 0x00 RW1C 14 LLINE1MIX [7:0] LLINE1MIX7 LLINE1MIX6 LLINE1MIX5 LLINE1MIX4 LLINE1MIX3 LLINE1MIX2 LLINE1MIX1 LLINE1MIX0 0x00 RW1C 15 RLINE1MIX [7:0] RLINE1MIX7 RLINE1MIX6 RLINE1MIX5 RLINE1MIX4 RLINE1MIX3 RLINE1MIX2 RLINE1MIX1 RLINE1MIX0 0x00 RW1C 16 LLINE2MIX [7:0] LLINE2MIX7 LLINE2MIX6 LLINE2MIX5 LLINE2MIX4 LLINE2MIX3 LLINE2MIX2 LLINE2MIX1 LLINE2MIX0 0x00 RW1C 17 RLINE2MIX [7:0] RLINE2MIX7 RLINE2MIX6 RLINE2MIX5 RLINE2MIX4 RLINE2MIX3 RLINE2MIX2 RLINE2MIX1 RLINE2MIX0 0x00 RW1C 18 LCDMIX [7:0] CDLMIX7 CDLMIX6 CDLMIX5 CDLMIX4 CDLMIX3 CDLMIX2 CDLMIX1 CDLMIX0 0x00 RW1C 19 RCDMIX [7:0] CDRMIX7 CDRMIX6 CDRMIX5 CDRMIX4 CDRMIX3 CDRMIX2 CDRMIX1 CDRMIX0 0x00 RW1C 1A LHPMIX [7:0] LHPMIX7 LHPMIX6 LHPMIX5 LHPMIX4 LHPMIX3 LHPMIX2 LHPMIX1 LHPMIX0 0x00 RW1C 1B RHPMIX [7:0] RHPMIX7 RHPMIX6 RHPMIX5 RHPMIX4 RHPMIX3 RHPMIX2 RHPMIX1 RHPMIX0 0x00 RW1C 1C EPMIX [7:0] EPMIX7 EPMIX6 EPMIX5 EPMIX4 EPMIX3 EPMIX2 EPMIX1 EPMIX0 0x00 RW1C 1D HP_CTRL [7:0] RESERVED POPTIME HPMOD HPOC 0x00 RW 1E HP_CTRL2 [7:0] RESERVED LVL_THR HIZ VOLIM RESERVED 0x00 RW 1F LS_CTRL [7:0] CDDRIVE DIRCD CDSM RCDBST LCDBST EDGE 0x00 RW 21 EPCONTROL [7:0] RESERVED MICB2GAIN MICB1GAIN EPGAIN 0x00 RW 22 MICBIAS_CTRL1 [7:0] VBATLOW MICB1LIM MICB1OCEN MICB1CURDEN MICB1SHT MICB1CURD 0x00 RW 23 MICBIAS_CTRL2 [7:0] RESERVED MICB2LIM MICB2OCEN MICB2CURDEN MICB2SHT MICB2CURD 0x00 RW 24 OUTPUT_ CONTROL [7:0] RNSM LNSM LDIFF LNFBEN ZCTO VMID 0x00 RW 25 PWDN_CTRL1 [7:0] LADCPDB RADCPDB MICB2PDB MICB1PDB AIN4PDB AIN3PDB AIN2PDB AIN1PDB 0x00 RW 26 PWDN_CTRL2 [7:0] LDAC2PDB RADC2PDB LDAC1PDB RDAC1PDB LLN2PDB RLN2PDB LLN1PDB RLN1PDB 0x00 RW 27 PWDN_CTRL3 [7:0] ZDPDB VBATPWDB RESERVED EPPDB LCDPDB RCDPDB HPPDB PWDB 0x00 RW 28 DPLLA_CTRL [7:0] DPLLA_REF_SEL DPLLA_NDIV 0x00 RW 29 PLLA_CTRL1 [7:0] PLLA_M_HI 0x00 RW 2A PLLA_CTRL2 [7:0] PLLA_M_LO 0x00 RW 2B PLLA_CTRL3 [7:0] PLLA_N_HI 0x00 RW 2C PLLA_CTRL4 [7:0] PLLA_N_LO 0x00 RW 2D PLLA_CTRL5 [7:0] RESERVED PLLA_R PLLA_X PLLA_TYPE 0x00 RW 2E PLLA_CTRL6 [7:0] RESERVED DPLLA_LOCKED PLLA_LOCKED DPLLA_BYPASS PLLA_EN 0x02 RW 2F DPLLB_CTRL [7:0] DPLLB_REF_SEL DPLLB_NDIV 0x00 RW 30 PLLB_CTRL1 [7:0] PLLB_M_HI 0x00 RW 31 PLLB_CTRL2 [7:0] PLLB_M_LO 0x00 RW 32 PLLB_CTRL3 [7:0] PLLB_N_HI 0x00 RW 33 PLLB_CTRL4 [7:0] PLLB_N_LO 0x00 RW 34 PLLB_CTRL5 [7:0] RESERVED PLLB_R PLLB_X PLLB_TYPE 0x00 RW 35 PLLB_CTRL6 [7:0] RESERVED DPLLB_LOCKED PLLB_LOCKED DPLLB_BYPASS PLLB_EN 0x02 RW 36 HEADDECT [7:0] RESERVED HEADSET 0x00 RW 37 ADC_DAC_ STATUS [7:0] RESERVED NOCLKDAC2 NOCLKDAC1 RESERVED NOCLKADC 0x00 R |
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