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ADAU1373BCBZ-R7 Datasheet(PDF) 1 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 1 Page - Analog Devices |
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1 / 296 page  Low Power Codec with Speaker and Headphone Amplifier ADAU1373 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. FEATURES 1 stereo ADC and 2 stereo DACs with sampling rates from 8 kHz to 48 kHz Low power: 7 mW record, 6 mW playback, 48 kHz at 1.8 V 8 single-ended or 4 differential inputs with PGA 2 microphone bias reference voltages with current sense 2 stereo digital microphone inputs Flexible analog input/output mixers 1 stereo differential or 2 stereo single-ended line outputs True ground-centered stereo Class-G headphone amplifier, capable of 2 × 50 mW into 16 Ω at 1.8 V, 10% THD Filterless stereo Class-D speaker amplifier, capable of 2 × 880 mW into 8 Ω at 3.6 V, 10% THD Differential earpiece amplifier capable of driving 32 Ω 2 PLLs, supporting input clocks from 8 kHz to 27 MHz I2C control interface Digital audio processing 3 digital audio input and output ports with ASRC I2S, PCM, right-justified, left-justified modes 4.05 mm × 3.82 mm, 81-ball, 0.4 mm pitch WLCSP package −40°C to +85°C operating temperature range APPLICATIONS Mobile phones, tablet PCs, e-books, portable media players GENERAL DESCRIPTION The ADAU1373 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback. The stereo audio ADCs and DACs support sampling rates from 8 kHz to 48 kHz, as well as a digital volume control. Eight single-ended or four differential analog inputs with PGAs are provided for adjusting the gain from −12 dB to +18 dB. They can be configured for microphones or line level signals. Two stereo digital microphone inputs are supported; four digital microphones can be connected in total. In addition, three serial digital audio input/output ports are provided with asynchronous sample rate converters (ASRCs) to support various sampling rates, allowing for flexible system design in mobile phone applications. The inputs can be mixed and selected before the ADC or con- figured to bypass the ADC. Two stereo DACs are included, with a flexible mixing option for routing the signals internally. The analog output side consists of line outputs, headphone output, speaker output, and receiver output. Two stereo single-ended line level outputs, which can be configured as two differential outputs, are included. The headphone output is stereo true ground centered (eliminating the need for coupling capacitors), with efficient Class-G (rail switching) architecture. The efficient stereo filterless Class-D switching amplifier provides ~1 W of stereo power for speakers. The differential receiver amplifier can be used to connect the separate receiver speaker. Two PLL blocks, which can lock to the inputs from 8 kHz to 27 MHz, are included. The DSP allows system designers to compensate for the real-world limitations of microphones, speakers, amplifiers, and listening environments, resulting in a dramatic improvement in perceived audio quality through equalization, multiband compression, and limiting algorithms. The SigmaStudio™ graphical development tool, which includes audio processing blocks such as filters, mixers, dynamics processors, and amplifiers for fast development of custom signal flows, is used to program the ADAU1373. FUNCTIONAL BLOCK DIAGRAM LINEOUT2 EARPIECE AMP ANALOG INPUTS ADC DAC1 DAC2 DIGITAL MICROPHONE SERIAL DIGITAL AUDIO INTERFACE A FDSP INPUT OUTPUT MUX HEADPHONE AMP SPEAKER AMP I2C PLLA GPIO BCLKA/BCLKB/BCLKC LRCLKA/LRCLKB/LRCLKC SDATAINA/SDATAINB/SDATAINC SDATAOUTA/SDATAOUTB/SDATAOUTC DMIC1_2_DATA DMIC3_4_DATA DMIC_CLK MICBIAS1, MICBIAS2 AIN1L/AIN1P TO AIN4L/AIN4P AIN1R/AIN1N TO AIN4R/AIN4N EPP EPN LOUT1L/LOUTLP, LOUT2L/LOUTLN LOUT1R/LOUTRP, LOUT2R/LOUTRN LN1FBIN, LN2FBIN HPL SGND HPR SPKLP SPKLN SPKRP SPKRN MUX MIX LINEOUT1 MUX MIX Figure 1. |
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