ADAU1373BCBZ-R7 datasheet(48/296 Pages) AD

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ADAU1373

Rev. 0 | Page 48 of 296

Table 11, Table 12, and Table 13 also list the typical PLL settings

at 44.1 kHz and 48 kHz sample rates. Note that the PLL control

setting in hexadecimal format represents the 48 bits (six bytes)

for either PLLA or PLLB. For PLLA, the six bytes should be written

starting from Register 0x29 through Register 0x2E. For PLLB,

the six bytes should be written starting from Register 0x30

through Register 0x35.

PLL Lock Acquisition

The core clock for the device is disabled until the core clock enable

bit (Bit 7, COREN) in Register 0x40 is set to 1. It is recommended

that the audio outputs not be turned on until PLL lock is

established.

To program the PLL during initialization or reconfiguration of

the clock setting, use the following procedure:

Bring the required blocks out of power-down (Register 0x25

to Register 0x27).

Ensure that the core clock is disabled (Register 0x40, Bit 7 = 0).

Enable the PLL (Register 0x2E, Bit 0, for PLLA; Register 0x35,

Bit 0, for PLLB).

Set the PLL control registers for the desired clock rate

(Register 0x28 to Register 0x2D for PLLA and Register 0x2F

to Register 0x34 for PLLB).

Poll the lock bit (Register 0x2E, Bit 2, and Register 0x35,

Bit 2, for APLL and Register 0x2E, Bit 3, and Register 0x35,

Bit 3, for DPLL). If the lock bit is set, proceed to Step 6;

otherwise, continue to poll. If no lock is established, check

the clock rate settings and clock to the device.

To ensure that the various blocks in the device are clocked

correctly, assert the core clock enable bit only after PLL

lock is acquired.

Table 11. Fractional PLL Parameter Settings for 44.1 kHz Base Sample Rate (PLL Output = 45.1584 MHz = 1024 × fS)

MCLK Input (MHz)

Input Divider (X)

Integer (R)

Denominator (M)

Numerator (N)

PLL Control Setting (Hex)

625

403

0x0271 0193 2901

625

477

0x0271 01DD 1901

8125

3849

0x1FBD 0F09 1901

14.4

125

0x007D 0022 3301

19.2

125

0x007D 0058 2301

19.68

1025

604

0x0401 025C 2301

19.8

1375

772

0x055F 0304 2301

625

477

0x0271 01DD 1B01

8125

3849

0x1FBD 0F09 1B01

1875

647

0x0753 0287 1B01

Table 12. Fractional PLL Parameter Settings for 48 kHz Base Sample Rate (PLL Output = 49.152 MHz = 1024 × fS)

MCLK Input (MHz)

Input Divider (X)

Integer (R)

Denominator (M)

Numerator (N)

PLL Control Setting (Hex)

125

0x007D 0012 3101

125

0x007D 000C 2101

1625

1269

0x0659 04F5 1901

14.4

0x004B 003E 3301

19.2

0x0019 0003 2B01

19.68

205

204

0x00CD 00CC 2301

19.8

825

796

0x0339 031C 2301

125

0x007D 000C 2301

1625

1269

0x0659 04F5 1B01

1125

721

0x0465 02D1 1B01

Table 13. Integer PLL Parameter Settings for fS = 48 kHz (PLL Output = 49.152 MHz = 1024 × fS)

MCLK Input (MHz)

Input Divider (X)

Integer (R)

Denominator (M)

Numerator (N)

PLL Control Setting (Hex)1

12.288

Don’t care

0xXXXX XXXX 2001

24.576

Don’t care

0xXXXX XXXX 1001

1 X = don’t care.

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