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ADAU1373BCBZ-R7 Datasheet(PDF) 13 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 296 page  ADAU1373 Rev. 0 | Page 13 of 296 Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL INPUT → DAC → MIXER → SPEAKER OUTPUT Dynamic Range 20 Hz to 20 kHz, −60 dBFS input, unweighted (rms) 93 dB 20 Hz to 20 kHz, −60 dBFS input, A-weighted (rms) 96 dB Signal-to-Noise Ratio 20 Hz to 20 kHz, A-weighted, relative to full scale 97 dB THD + N At −1 dBFS, 1 kHz 0.01 % Interchannel Isolation 100 dB Interchannel Phase Deviation 0.1 Degrees Digital Volume Control Step 0.375 dB Range 95 dB DIGITAL INPUT → DAC → MIXER → EARPIECE OUTPUT Dynamic Range 20 Hz to 20 kHz, −60 dBFS input, unweighted (rms) 93 dB 20 Hz to 20 kHz, −60 dBFS input, A-weighted (rms) 96 dB Signal-to-Noise Ratio 20 Hz to 20 kHz, A-weighted, relative to full scale 97 dB THD + N At −1 dBFS, 1 kHz 0.1 % Full-Scale Output Voltage Scales linearly with SPKVDD; SPKVDD = 3.6 V 1.53 V rms Digital Volume Control Step 0.375 dB Range 95 dB REFERENCE Common-Mode Reference Output CM pin AVDD/2 V CHARGE PUMP Supply Voltage 1.62 1.8 1.98 V Outputs CPVDD Below Supply Switching Threshold 0.9 V Above Supply Switching Threshold 1.8 V CPVSS Below Supply Switching Threshold −0.9 V Above Supply Switching Threshold −1.8 V Switching Frequency 500 kHz Flying Capacitor Value 0.47 1 10 μF Supply Switching Threshold 0.4 V Start-Up Time 0.5 ms PLLx Input Frequency 0.008 27 MHz Lock Time (Analog PLL) 3 ms Jitter (Cycle-to-Cycle) rms Measured at GPIOx with master clock output set at 256 × fS (12.288 MHz, where fS = 48 kHz) Analog PLL Only (DPLL Bypassed) 8 MHz Input (Fractional Mode) 470 ps 27 MHz Input (Fractional Mode) 280 ps 12.288 MHz Input (Integer Mode) 200 ps Digital PLL + Analog PLL 8 kHz LRCLKx Input 310 ps 96 kHz LRCLKx Input 260 ps 512 kHz (8 kHz × 64) BCLKx Input 310 ps 2.048 MHz (8 kHz × 256) MCLKx Input 210 ps MCLKx Clock Output Frequency 49.152 MHz GPIOx Drive Capability IOVDDx = 1.8 V 4 mA IOVDDx = 3.3 V 20 mA |
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