ADAU1373BCBZ-R7 datasheet(53/296 Pages) AD

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ADAU1373

Rev. 0 | Page 53 of 296

DIGITAL AUDIO INTERFACE

The ADAU1373 provides three digital audio interface ports:

Digital Audio Interface A, Digital Audio Interface B, and Digital

Audio Interface C. Each port can receive and transmit audio data in

various serial formats. The ports can be configured as master or

slave, accommodating many possible system design combinations.

Each port has a frame clock (LRCLKA to LRCLKC), a bit clock

(BCLKA to BCLKC), and data receive and data transmit pins

(SDATAINA to SDATAINC and SDATAOUTA to SDATAOUTC)

available. The possible serial audio data formats are right justified,

left justified, I2S, and DSP mode. The format for the ports can be

set using Register 0x44 for Digital Audio Interface A, Register 0x45

for Digital Audio Interface B, and Register 0x46 for Digital Audio

Interface C. The serial data is received or transmitted MSB first,

followed by the remaining data bits. For more information about

the serial data input/output formats, see Figure 98 to Figure 100.

The registers allow each port to be set independently, as either

master or slave. In addition, these registers provide controls for

bit clock polarity, swapping left/right data, inverting the frame

clock, and adjusting data width. Figure 97 shows the audio

interface and ASRC block diagram.

Digital Audio Interface A, Digital Audio Interface B, and Digital

Audio Interface C can go through the ASRC or directly to the

internal digital engine. The ASRCs on each port allow system

design flexibility to accommodate sample rates at the ports that

are different from those accommodated by the internal DSP.

The digital audio interface ports can be independently configured

as master or slave by using the MSx bit (Bit 6) in Register 0x44,

Digital Audio Interface B, and Digital Audio Interface C, respec-

tively. This allows a number of different options for using the

three ports.

When the ports are configured in master mode, the ports derive

the bit clock and frame clock using either AIFCLKA or AIFCLKB,

which are derived from PLLA and PLLB, respectively. The sample

rate can be selected using Bits[4:2] in Register 0x47, Register 0x48,

and Register 0x49 for Digital Audio Interface A, Digital Audio

Interface B, and Digital Audio Interface C, respectively.

In slave mode, the port accepts the bit clock and the frame clock

from the master in the system. If the ASRCs are enabled, the

port is not required to be synchronous to the master clock.

However, if the ASRCs are disabled, ensure that the port is

synchronous to the master in the system by providing the

master clock from the respective master.

fS_A_EXT

ASRCA

DSP

DAC1

DAC2

ADC/

DMCA

DMCB

MIX/MUX

DIGITAL

AUDIO

INTERFACE A

AIFA_REC

AIFA_PB

AIFB_REC

AIFB_PB

AIFC_REC

AIFC_PB

FDSP_CH2_DOUT

FDSP_CH2_DIN

FDSP_CH3_DOUT

FDSP_CH3_DIN

FDSP_CH4_DOUT

FDSP_CH4_DIN

FDSP CLK (128 × fS)

ASRC CLK

(256 ×

fS)

BCLKA

DOUT_A

DIN_A

fS_A_INT

BCLK_A

DOUT_A

DIN_A

fS_DSP

BCLK_DSP

DOUT_DSP

DIN_DSP

fS_B_EXT

ASRCB

DIGITAL

AUDIO

INTERFACE B

BCLK_B

DOUT_B

DIN_B

fS_B_INT

BCLK_B

DOUT_B

DIN_B

fS_DSP

BCLK_DSP

DOUT_DSP

DIN_DSP

fS_C_EXT

ASRCC

DIGITAL

AUDIO

INTERFACE C

AIFCLKA

AIFCLKB

(256 ×

fS)

BCLK_C

DOUT_C

DIN_C

fS_C_INT

BCLK_C

DOUT_C

DIN_C

fS_DSP

BCLK_DSP

DOUT_DSP

DIN_DSP

CODEC

ENGINE

Figure 97. Digital Audio Interface and ASRC Block Diagram

ADAU1373BCBZ-R7 Datasheet(PDF) 53 Page - Analog Devices

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