ADAU1373BCBZ-R7 datasheet(60/296 Pages) AD

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ADAU1373

Rev. 0 | Page 60 of 296

–14

–16

–18

–20

–22

0.2

–1.0

–0.5

0.5

1.0

0.1

–0.1

–0.2

1000

2000

3000

4000

5000

6000

7000

8000

DRC GAIN (dB)

OUTPUT

INPUT

RELEASE (DECAY) TIME

(NO HOLD TIME)

(DRCTHY1)

LIMITER TARGET LEVEL

(DRCTHY1)

ATTACK TIME

(DRCLELATT)

LIMITER THRESHOLD

(DRCTHX1)

Figure 108. Limiter Dynamic Behavior—Working Example

OUTPUT

–14

–15

–18

–17

–16

–19

–20

–21

1000

2000

3000

4000

5000

6000

7000

8000

DRC GAIN (dB)

HOLD TIME DURING

RECOVERY

(DRCHTNOR)

0.2

–1.0

–0.5

0.5

1.0

0.1

–0.1

–0.2

INPUT

Figure 109. Limiter Dynamic—Working Example Showing Hold Time

1000

2000

3000

4000

5000

6000

4000

5000

6000

1000

2000

3000

4000

5000

6000

DRC GAIN (dB)

–1

–2

–10

–20

–30

INPUT

NOISE GATE

THRESHOLD

(DRCTHX4)

1.0

0.5

–0.5

–1.0

NOISE GATE RECOVERY

(DECAY) TIME

HOLD

TIME FOR

NOISE GATE

x10–4

OUTPUT

ATTACK

TIME

3000

1000

2000

Figure 110. Noise Gate Dynamic—Working Example

Working Example

If the required LPF cutoff frequency is 20 kHz, the HPF cutoff

frequency is 350 Hz, low band crossover frequency is 1 kHz, and

high band crossover frequency is 8 kHz, as shown in Figure 111.

H(f)

350

20000

8000

1000

fIN (Hz)

LOW

BAND

MID

BAND

HIGH

BAND

Figure 111. MDRC Example

The DRC can generate an interrupt request when enabled. See

Table 21 for a listing of the interrupt request register and bit

controls.

•

To configure MDRC HPF and LPF, set Register 0xB0 to 0x1A.

•

To configure MDRC crossover frequencies, set Register 0xB1

to 0x79.

•

To enable MDRC HPF and LPF, set Register 0xB2 to 0x07.

Table 21. Interrupt Request Register and Bit Controls

Address

Bits

Bit Name

Function

0x8F, 0x9F, 0xAF

DRCIRQ_MODE

DRC interrupt mode. 0: selects the input signal rms value as the interrupt source; 1: selects the

ratio between the peak and rms signal of the input signal.

0x8F, 0x9F, 0xAF

DRCIRQ_EN

DRC interrupt enable.

0x8E, 0x9E, 0xAE

[6:2]

SIG_DET_RMS

RMS detector level. Defines the rms value above which the IRQ circuits send out the

interruption signal when the DRCIRQ_MODE bit = 0. Available range: −76.5 dB to −30 dB.

0x8E, 0x9E, 0xAE

[1:0]

SIG_DET_PK

Peak to rms detector ratio. Defines the peak to rms value above which the IRQ circuits send

out the interruption signal when the DRCIRQ_MODE bit = 1. Available range: 12 dB to 30 dB.

ADAU1373BCBZ-R7 Datasheet(PDF) 60 Page - Analog Devices

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