ADAU1373BCBZ-R7 datasheet(71/296 Pages) AD

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ADAU1373

Rev. 0 | Page 71 of 296

Addressing

Initially, each device on the I2C bus is in an idle state and monitors

the SDA and SCL lines for a start condition and the correct address.

The I2C master initiates a data transfer by establishing a start

condition, defined by a high-to-low transition on SDA while SCL

remains high. This indicates that an address/data stream follows.

All devices on the bus respond to the start condition and shift

the next eight bits (the 7-bit address plus the R/W bit), MSB first.

The device that recognizes the transmitted address responds by

pulling the data line low during the ninth clock pulse. This ninth

bit is known as an acknowledge bit. All other devices withdraw

from the bus at this point and return to the idle condition.

The R/W bit determines the direction of the data. A Logic 0 on

the LSB of the first byte means that the master writes information

to the peripheral, whereas a Logic 1 means that the master reads

information from the peripheral after writing the subaddress and

repeating the start address. A data transfer takes place until a stop

condition is encountered. A stop condition occurs when SDA

transitions from low to high while SCL is held high.

shows the timing of an I2C single-byte write, and

shows the timing of an I2C single-byte read.

Figure 117

Figure 118

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence with

normal read and write operations, the ADAU1373 immediately

jumps to the idle condition. During a given SCL high period,

the user should issue only one start condition, one stop condition,

or a single stop condition followed by a single start condition. If

an invalid subaddress is issued by the user, the ADAU1373 does

not issue an acknowledge and returns to the idle condition.

If the user exceeds the highest subaddress while in autoincrement

mode, one of two actions is taken. In read mode, the ADAU1373

outputs the highest subaddress register contents until the master

device issues a no acknowledge, indicating the end of a read. In

a no acknowledge condition, the SDA line is not pulled low on

the ninth clock pulse on SCL. If the highest subaddress location

is reached while in write mode, the data for the invalid byte is

not loaded into any subaddress register, a no acknowledge is

issued by the ADAU1373, and the part returns to the idle

condition.

R/W

SCL

SDA

SCL

(CONTINUED)

SDA

(CONTINUED)

FRAME 1

DEVICE ADDRESS BYTE

FRAME 3

DATA BYTE

START BY

MASTER

STOP BY

MASTER

ACK BY

ADAU1373

ACK BY

ADAU1373

ACK BY

ADAU1373

FRAME 2

Figure 117. I2C Single Byte Write

SCL

SDA

SCL

(CONTINUED)

SDA

(CONTINUED)

START BY

MASTER

STOP BY

MASTER

ACK BY

MASTER

ACK BY

ADAU1373

ACK BY

ADAU1373

ACK BY

ADAU1373

R/W

DEVICE ADDRESS

FRAME 2

FRAME 1

DEVICE ADDRESS BYTE

REPEATED

START BY MASTER

FRAME 3

DEVICE ADDRESS BYTE

FRAME 4

READ DATA BYTE

Figure 118. I2C Single Byte Read

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