ADAU1373BCBZ-R7 datasheet(47/296 Pages) AD

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ADAU1373

Rev. 0 | Page 47 of 296

DPLL

The DPLL consists of a phase comparator, followed by a high-

pass filter and integrators. The following equation shows the

relationship of input-to-output frequency:

fOUT = (fIN/ND) × MD

where:

fOUT is the DPLL output frequency (8 MHz to 27 MHz).

fIN is the DPLL input frequency (8 kHz to 8 MHz).

ND is the divider. It can be set to 1, 2, 4, 8, 16, 32, 64, 128, 256, 512,

or 1024, using Bits[3:0] (DPLLA_NDIV) in Register 0x28 for

DPLLA and Bits[3:0] (DPLLB_NDIV) Register 0x2F for DPLLB.

MD is the multiplier (fixed internally to 1024).

DPLL Divider Example

fIN = 8 kHz

fOUT = 8 MHz

ND = 8 × 1024/8 = 1.024

Setting ND to 1 results in fOUT ≥ 8 MHz. Therefore, ND should

be set to 1.

Core Clock

The core clock is derived directly from the external clock at the

MCLK1 or MCLK2 pins or from the PLL. The PLLA_EN bit for

PLLA (Bit 0 in Address 0x2E) and the PLLB_EN bit for PLLB

(Bit 0 in Address 0x35) can be used to enable or disable the

PLL. Clocks for the converters, the serial ports, and the DSP are

derived from the core clock. The core clock rate is always an

integer multiple of the desired sample rate used inside the part.

Case 1—PLL Bypassed (Using External Clock as Core Clock)

If the PLL is bypassed, the clock available at MCLK1 (Ball C2)

or MCLK2 (Ball D1) is used as the core clock. Therefore, fCORE = fIN.

As the PLL is bypassed, the frequency of the clock at the MCLKx

pins must be set properly, using the clock divider bits, CLK1SDIV,

Bits[5:3], and MCLK1DIV, Bits[2:0], in Register 0x40 for PLLA and

CLK2SDIV, Bits[5:3], and MCLK2DIV, Bits[2:0] in Register 0x42

for PLLB. The required external clock rate can be determined by

the following equation, in which J and K are the clock dividers:

fIN = 256 × fS × (J + 1) × (K + 1)

See Table 14, Table 15, and Table 16 for some possible options

for external clock rates. Note that clock rates greater than 50 MHz

require careful attention to the clock driver and board layout to

maintain signal integrity.

Be sure that this clock is available to the MCLKx input pins

before enabling the COREN bit (Bit 7, core clock enable) in

Case 2—PLL Enabled

The internal PLL can be used to generate the core clock from

the external clock. The internal PLL has two modes of operation:

integer mode and fractional mode. Therefore, fCORE = fPLL.

APLL

The APLL provides the fine resolution required to generate clocks

for the internal blocks. It uses either the clock input at the MCLK1

pin (Ball C2) or a DPLL output as a reference to generate the core

clock. The PLL can be set for either integer or fractional mode.

The PLL multiplier and divider (X, R, M, and N) are programmed

using Register 0x29 to Register 0x2D for PLLA and Register 0x30

to Register 0x34 for PLLB. The PLL can accept input frequencies in

the range of 8 MHz to 27 MHz, either directly from an external

source, if the external clock input is greater than 8 MHz, or from

the DPLL, if the external clock input is within a range of 8 kHz

to 8 MHz. The PLL lock range is 45.158 MHz to 49.152 MHz.

This sets the PLL output frequency based on the sample rate

governed by the following equation:

fPLL = 256 × fS × (J + 1) × (K + 1)

where J, K = 0, 1, 2, …7.

fIN

÷X

TO PLL

CLOCK DIVIDER

× (R + N/M)

Figure 94. APLL Block Diagram

The APLL can be used in either integer mode or fractional mode.

Integer Mode

Integer mode is used when the MCLK frequency is an integer

multiple of the PLL output (1024 × fS) frequency, governed by

the following equation:

fPLL = (R/X) × fIN

where fPLL = 1024 × fS

For example, if fIN = 12.288 MHz and fS = 48 kHz, then

fPLL (PLL Required Output) = 1024 × 48 kHz = 49.152 MHz

R/X = 49.152 MHz/12.288 MHz = 4

Therefore, R and X are set as follows: R = 4, and X = 1 (default).

In integer mode, the values set for N and M are ignored. Table 13

shows common integer PLL parameter settings for fS = 48 kHz

sampling rates.

Fractional Mode

Fractional mode is used when the available MCLK is a fractional

multiple of the desired PLL output; it is governed by the following:

fPLL = fIN × (R + (N/M))/X

For example, MCLK = 12 MHz and fS = 48 kHz.

The PLL output is 1024 × fS.

PLL Output = 1024 × 48 kHz = 49.152 MHz

To find the values of R, N, and M, use the following equation:

fPLL = fIN × (R + (N/M))/X

where fPLL = 49.152, and fIN = 12 MHz.

(R + (N/M))/X = 49.152 MHz/12 MHz = 4 + (12/125)

See Table 11 and Table 12 for common fractional PLL parameter

settings for 44.1 kHz and 48 kHz sampling rates.

ADAU1373BCBZ-R7 Datasheet(PDF) 47 Page - Analog Devices

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