ADAU1373BCBZ-R7 datasheet(69/296 Pages) AD

69 / 296 page

ADAU1373

Rev. 0 | Page 69 of 296

INTERRUPT REQUEST (IRQ)

The ADAU1373 can generate an interrupt request based on

selected events from the various internal blocks. The interrupt

controller receives inputs from the MICBIAS current detect,

ASRC unlock detect, DRC signal activity detect, PLL unlock

detect, jack detect, and analog fault detect. Three registers are

provided for this function: Register 0xE5 can be used to set the

mask for the interrupts, Register 0xE6 stores the raw status

of the interrupts, and Register 0xE7 stores the status of the

interrupts after mask. The generation of interrupts can be

enabled or disabled using Register 0xE8, Bit 0.

The interrupts can be masked using the respective bits in

the interrupt request. The faults are reported in Register 0xE7.

When faults are unmasked, the status bits in Register 0xE7 are

latched until 1 is written to them. The raw status of the faults

can be read in Register 0xE6.

In addition, any of the above interrupts can be used to initiate the

IRQ (interrupt request) on the GPIOx pins. The four GPIO pins

can be set for IRQ function using Register 0xE3 and Register 0xE4.

The following events are reported in the interrupt status register

(Register 0xE6, IRQ_RAW):

•

Unlocking of any of the three ASRCs. When either of the

three ASRC loses lock, the respective ASRCx_IRQ_RAW_

STATE bit is set.

•

The DRC input level exceeding the threshold set in

sets the DRC_IRQ_RAW_STATE.

•

The on-chip PLL losing lock, which sets the PLL_UNLOCK_

RAW_STATE bit.

•

Any write to Register 0x36, Bits[1:0], which sets the

HP_CFG_RAW_STATE bit.

•

A change in the logic level at the JACKDET pin, which sets

the HP_DECT_RAW_STATE bit.

•

Occurrence of an analog fault, which sets the AFAULT_

RAW_STATE bit.

The following analog faults can set the AFAULT_RAW_STATE bit:

•

Earpiece amplifier overcurrent

•

Speaker amplifier left channel overcurrent

•

Speaker amplifier right channel overcurrent

•

Headphone amplifier overcurrent or overtemperature

The overcurrent thresholds are fixed internally. The overtem-

perature fault is set when the die temperature exceeds 150°C ±

15°C.

The IRQs can be reported via GPIOx, or the IRQ_STATE register

(Register 0xE7) can be read via the I2C to determine which block

is reporting a fault. The analog fault status in Register 0xE7 can be

used in conjunction with Register 0x39 or Register 0x38 to

differentiate among the analog faults.

amplifier overcurrent, headphone amplifier overcurrent, and

die overtemperature.

In addition, Register 0x38 reports Microphone Bias 1 and Micro-

phone Bias 2 current detect, as well as overcurrent and logic

voltage changes at the JACKDET pin (Ball G5).

The MICB1THS and MICB2THS bits (Register 0x38, Bit 0 and

Bit 2, respectively) can be used to detect the connection of the

electret microphone at the MICBIASx pins (Ball C8 and Ball C9).

When the electrets microphone is connected, the current flow from

the MICBIASx pins to the microphone is detected. The current

detection threshold can be set using Register 0x22. Four settings

are provided: 150 μA (default), 330 μA, 510 μA, and 700 μA.

Similarly, the overcurrent at the MICBIASx outputs can be

detected. This allows for limiting the current drawn out of the

internal microphone bias regulator in case of a short circuit at

the MICBIASx pin. The overcurrent limit can be set to 330 μA,

700 μA, 1000 μA, or 1400 μA. The JACKDECT bit (Register 0x38,

Bit 4) can be used to detect the insertion/ removal of the accessory

at the headphone socket. When jack insertion is detected, the

status bit is set to 1.

The ADC/DAC clock loss is reported in Register 0x37.

ADAU1373BCBZ-R7 Datasheet(PDF) 69 Page - Analog Devices

ADAU1373BCBZ-R7 Datasheet(HTML) 69 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL