ADAU1373BCBZ-R7 datasheet(61/296 Pages) AD

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ADAU1373

Rev. 0 | Page 61 of 296

BIQUAD1

BIQUAD2

BIQUAD3

BIQUAD4

BIQUAD5

FIRST-

ORDER

IIR 1

FIRST-

ORDER

IIR 1

SEVEN-BAND EQUALIZER

Figure 112. Seven-Band Equalizer Block Diagram

PROGRAMMABLE SEVEN-BAND EQUALIZER

The programmable seven-band equalizer is composed of five

biquad filters (Band 1 to Band 5) and two first-order IIR filters

(Band 6 and Band 7). See Figure 112 for a system block diagram.

The EQ shares Register 0x80 through Register 0xBD with the

MDRC. All the filter coefficients are programmable via the

corresponding registers. The filter bank can also be configured

as some other filters, including de-emphasis and notch filter,

when all five midfrequency bands are not needed.

Table 22. Register 0x80 to Register 0xBD EQ Coefficients

Address

Bit Name

Descripton

0x80

EQ1_COEF0_HI[15:8]

EQ Band 1, Coefficient 0 MSB

0x81

EQ1_COEF0_LO[7:0]

EQ Band 1, Coefficient 0 LSB

0x82

EQ1_COEF1_HI[15:8]

EQ Band 1, Coefficient 1 MSB

0x83

EQ1_COEF1_LO[7:0]

EQ Band 1, Coefficient 1 LSB

0x84

EQ1_COEF2_HI[15:8]

EQ Band 1, Coefficient 2 MSB

0x85

EQ1_COEF2_LO[7:0]

EQ Band 1, Coefficient 2 LSB

...

0xBC

EQ7_COEF2_HI[15:8]

EQ Band 7, Coefficient 2 MSB

0xBD

EQ7_COEF2_LO[7:0]

EQ Band 7, Coefficient 2 LSB

To operate as a seven-band equalizer, the two first-order IIR filters

are usually configured as one low-pass shelving filter and one

high-pass shelving filter, and the biquad filters are configured as

peak filters.

The first-order IIR filter cutoff frequency and gain are adjustable

using the filter coefficient registers. In addition, the five biquad

filters have adjustable gain, the center frequency for the peak

filters, or cutoff frequency for shelving filters. For a frequency

band that is <200 Hz, the low-pass shelving filter is

recommended instead of a peak filter.

The biquad common peaking filter transfer function for Band 1

through Band 5 is as follows:

)

(

−

The shelving filter transfer function for Band 6 and Band 7 is

)

(

−

The filter coefficients can be calculated using the previous two

equations or by using the GUI provided. See the Register

Map—EQ Coefficients section for register addresses.

EQ_FORMAT bit (Register 0xBE, Bit 2) defines the coefficient

bit format. The default setting is 0, and the corresponding format

is Q3.13. In this default mode, the supported coefficients range

from −4 ~ +4. For equalization, this range means that the cutoff/

center frequencies can vary from 40 Hz to 12 kHz when the input

sampling rate is 48 kHz, and peak gain varies from −18 dB to

+18 dB. When Register 0xBE, Bit 2 = 1, the EQ format changes

to Q4.12 to achieve a larger coefficient range (from −8 ~ +8).

This mode enables larger gain boost or cut range.

On-the-fly coefficient updates are supported. If the filter bank

coefficients are updated in this mode, the EQ_UPD bit (Bit 1,

finishes. This setting updates the filter coefficients for the filter

desired. The coefficient update procedure takes about 0.05 ms.

The EQ_UPDING bit (Bit 4, Register 0xBE) is a read-only bit

that represents the coefficient update status. This bit should be

read to check the status of the coefficient update process. When

the EQ_UPDING bit is set to 1, the update is in process; when

the EQ_UPDING bit is set to 0, the update is complete.

If the system clock is lost during the updating period, the update

procedure cannot be completed and, in such a case, it is recom-

mended that the EQ_UPD_CLR bit (Bit 3, Register 0xBE) be set

to 1 to cancel the update.

These addresses are also used by other registers. Therefore, when

the EQ coefficient read/write access is required, the write/read

enable bit, EQ_WR_EN (Register 0xBE, Bit 0), should be set to 1.

the filter bank can be disabled, and all of the seven bands can be

bypassed. Bit EQEN and Bit EQBP7 to Bit EQBP1 in Register 0xBF

can be used to enable or disable the desired EQ band.

ADAU1373BCBZ-R7 Datasheet(PDF) 61 Page - Analog Devices

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