ADAU1373BCBZ-R7 datasheet(49/296 Pages) AD

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ADAU1373

Rev. 0 | Page 49 of 296

SAMPLING RATES

The ADCs, DACs, and DSP share a common sampling rate (fS)

that is determined based on the core clock rate. Three digital

audio interface ports are available for the ADAU1373. Each port

is provided with an asynchronous sample rate converter (ASRC).

If the ASRCs are used, the sample rate at the digital ports can be

different from the internal sample rate. However, the sample rate

used internally must be equal to or higher than the sample rate

at the ports.

SETTING THE PLL AND CLOCK RATES

For proper operation of the ADAU1373, the device must be set

for correct clock rates. Following are the recommended steps:

Step 1—Sample Rate (fS)

Determine the desired operating sample rate (fS) for the internal

blocks. fS is based on either 48 kHz (48 kHz, 32 kHz, 24 kHz,

16 kHz, 8 kHz) or 44.1 kHz (44.1 kHz, 22.05 kHz, 11.025 kHz,

8.0182 kHz). If the ASRCs are bypassed, this is the operating

sample rate at Digital Audio Interface A, Digital Audio Interface B,

and Digital Audio Interface C.

Step 2—Determine Divider J and Divider K

The PLL output or external clock input is divided down to get

the required 256 × fS core clock. Two clock dividers (CLK1SDIV,

Bits[5:3], and MCLK1DIV, Bits[2:0] in Register 0x40 for PLLA and

CLK2SDIV, Bits[5:3], and MCLK2DIV, Bits[2:0] in Register 0x42

for PLLB) are provided; each clock divider can be set from 1 to 8.

The CLKxSDIV bits set the K value, and the MCLKxDIV bits

set the J value of the divider. See Figure 93 for more details. See

Table 14, Table 15, and Table 16 for some possible options.

Next, depending on the whether the direct external clock or

PLL is used, select the appropriate equation from the following

sections.

External Mode

In the external mode, the external clock frequency determines

the internal device operation clock rate.

If using external mode,

fIN = 256 × D × fS

where D = (J + 1) × (K + 1).

For external clock use, see Table 14, Table 15, and Table 16 for

some possible choices.

Note that clock input frequencies above 50 MHz, although

possible, require careful attention—especially on clock driver

and board layout to maintain signal integrity and lower EMI.

Table 14. 48 kHz Sample Rate (fS)

Input MCLK

Divider

Divider Ratio

Divider

Divider Ratio

fIN

CLKxSDIV, Bits[5:3]

K = 0

K + 1

MCLKxDIV, Bits[5:3]

J + 1

256 × fS (12.288 MHz)

000

512 × fS (24.576 MHz)

000

001

768 × fS (36.864 MHz)

000

010

1024 × fS (49.152 MHz)

000

011

Table 15. 44.1 kHz Sample Rate (fS)

Input MCLK

Divider

Divider Ratio

Divider

Divider Ratio

fIN

CLKxSDIV, Bits[5:3]

K = 0

K + 1

MCLKxDIV, Bits[5:3]

J + 1

256 × fS (11.289 MHz)

000

512 × fS (22.5792 MHz)

000

001

768 × fS (33.8688 MHz)

000

010

1024 × fS (45.1584 MHz)

000

011

Table 16. 32 kHz Sample Rate (fS)

Input MCLK

Divider

Divider Ratio

Divider

Divider Ratio

fIN

CLKxSDIV, Bits[5:3]

K = 0

K + 1

MCLKxDIV, Bits[5:3]

J + 1

256 × fS (8.192 MHz)

000

512 × fS (16.384 MHz)

000

001

768 × fS (24.576 MHz)

000

010

1024 × fS (32.768 MHz)

000

011

1280 × fS (40.96 MHz)

000

100

1536 × fS (49.152 MHz)

000

101

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