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ADAU1373BCBZ-R7 Datasheet(PDF) 59 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 59 Page - Analog Devices |
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59 / 296 page  ADAU1373 Rev. 0 | Page 59 of 296 The DRCs consist of both peak and rms signal detectors. Either the peak or the rms detector can be assigned for noise gate, compressor/expander, and limiter. Bits[5:3] in Register 0x8D, Register 0x9D, and Register 0xAD are provided for selecting the detectors, as follows: • The DRCNGSRC bit (Bit 5) can be used for selecting the noise gate detector. • The DRCCESRC bit (Bit 4) can be used for selecting the compressor/expander detector. • The DRCLMSRC bit (Bit 3) can be used for selecting the limiter detector. The DRC can be set to function as limiter, compressor, expander, or noise gate. See Figure 107 for the input/output plot showing the various modes of operation of the DRC. The DRC allows flexibility in setting up the thresholds, as well as attack and release time controls. The DRC allows independent adjustment of the thresholds by providing control of the x-axis and y-axis using Register 0x82 to Register 0x89 for DRC1, Register 0x92 to Register 0x99 for DRC2, and Register 0xA2 to Register 0xA9 for DRC3. Bit DRCTHX1 to Bit DRCTHX4 in these registers can be used to set the input level threshold point on the x-axis, and Bit DRCTHY1 to Bit DRCTHY4 can be used to set the output level point on the y-axis. The available range is −96 dB to 0 dB for each threshold. OUTPUT DRCTHY1 DRCTHY2 DRCTHY3 DRCTHY4 LIMITER COMPRESSOR POINT1 POINT2 POINT3 POINT4 EXPANDER NOISE GATE INPUT DRCTHX4 DRCTHX3 DRCTHX2 DRCTHX1 Figure 107. DRC Output vs. Input Plot The DRC gain can be set using the DRCG bits (Bits[5:2]) in Register 0x8C, Register 0x9C, and Register 0xAC. The range available is −24 dB to +21 dB. See Table 19 for a listing of the DRC detector selection registers and bits and their functions. Table 20 lists the registers and bits that control the dynamic behavior of the DRC. Table 19. DRC Setting Bits and Functions Register Address Bits Bit Name Description 0x8C, 0x9C, 0xAC [5:2] DRCG Sets the DRC gain; available range is from −24 dB to +21 dB. 0x8D, 0x9D, 0xAD 7 DRCNGTGT Sets the DRC noise gate target. 0x8D, 0x9D, 0xAD 6 DRCNGHDEN Enables or disables the DRC noise gate recovery hold. 0x8D, 0x9D, 0xAD 5 DRCNGSRC Selects the DRC noise gate level detector; selects either rms or peak detector. 0x8D, 0x9D, 0xAD 4 DRCCESRC Selects the DRC compressor/expander level detector; selects either rms or peak detector. 0x8D, 0x9D, 0xAD 3 DRCLMSRC Selects the DRC limiter level detector; selects either rms or peak detector. 0x8D, 0x9D, 0xAD 2 DRCNGEN Noise gate enable control; provides independent noise gate control. 0x8D, 0x9D, 0xAD [1:0] DRCEN DRC enable control; enables or disables the DRC. The input source for the DRC can be selected as left channel, right channel, or both. Table 20. DRC Dynamic Behavior Control Register Address Bits Bit Name Description 0x80, 0x90, 0xA0 [3:0] DRCLELTAV Sets rms signal detector averaging time. Available range is from 750 μs to 24.576 sec. 0x81, 0x91, 0xA1 [7:4] DRCLELATT Sets DRC attack time. Available range is 46.875 μs to 1.536 sec. 0x81, 0x91, 0xA1 [3:0] DRCLELDEC Sets DRC decay (release) time. Available range is 0.75 ms to 24.576 sec. 0x8A, 0x9A, 0xAA [7:4] DRCGSATT Sets DRC gain smooth attack time. Available range is 46.875 μs to 1.536 sec. 0x8A, 0x9A, 0xAA [3:0] DRCGSDEC Sets DRC gain smooth decay time. Available range is 0.75 ms to 24.576 sec. 0x8B, 0x9B, 0xAB [7:4] DRCHTNOR Sets DRC normal operation hold time. Available range is from 0 ms up to 1.37 sec; value increments by 2× the previous value, beginning with 0.67 ms. 0x8B, 0x9B, 0xAB [3:0] DRCHTNG Sets DRC noise gate hold time. Available range is from 0 ms up to 1.37 sec; value increments by 2× the previous value, beginning with 0.67 ms. |
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