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ADAU1373BCBZ-R7 Datasheet(PDF) 51 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 51 Page - Analog Devices |
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51 / 296 page  ADAU1373 Rev. 0 | Page 51 of 296 Table 17. PLL Control Register Summary Reg Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x28 DPLLA_CTRL DPLLA_REF_SEL DPLLA_NDIV 0x00 RW 0x29 PLLA_CTRL1 PLLA_M_HI 0x00 RW 0x2A PLLA_CTRL2 PLLA_M_LO 0x00 RW 0x2B PLLA_CTRL3 PLLA_N_HI 0x00 RW 0x2C PLLA_CTRL4 PLLA_N_LO 0x00 RW 0x2D PLLA_CTRL5 RESERVED PLLA_R PLLA_X PLLA_TYPE 0x00 RW 0x2E PLLA_CTRL6 RESERVED DPLLA_LOCKED PLLA_LOCKED DPLLA_BYPASS PLLA_EN 0x10 RW 0x2F DPLLB_CTRL DPLLB_REF_SEL DPLLB_NDIV 0x00 RW 0x30 PLLB_CTRL1 PLLB_M_HI 0x00 RW 0x31 PLLB_CTRL2 PLLB_M_LO 0x00 RW 0x32 PLLB_CTRL3 PLLB_N_HI 0x00 RW 0x33 PLLB_CTRL4 PLLB_N_LO 0x00 RW 0x34 PLLB_CTRL5 RESERVED PLLB_R PLLB_X PLLB_TYPE 0x00 RW 0x35 PLLB_CTRL6 RESERVED DPLLB_LOCKED PLLB_LOCKED DPLLB_BYPASS PLLB_EN 0x02 RW 0x40 CLK1_ SOURCE_DIV COREN CLK1S_SEL CLK1SDIV MCLK1DIV 0x00 MMRW 0x41 CLK1_ OUTPUT_DIV RESERVED CLK1OEN CLK1ODIV 0x00 RW 0x42 CLK2_ SOURCE_DIV CLK2EN CLK2S_SEL CLK2SDIV MCLK2DIV 0x00 MMRW 0x43 CLK2_ OUTPUT_DIV RESERVED CLK2OEN CLK2ODIV 0x00 RW Table 18. PLLA/PLLB Control Register Settings (PLLA: Register 0x28 to Register 0x2E; PLLB: Register 0x2F to Register 0x35) Bits Bit Name Settings Description [47:32] PLLx_M_HI[7:0], PLLx_M_LO[7:0] Denominator of the fractional APLL: a 16-bit binary number. The PLLA/PLLB Control M value can be set using Register 0x29 and Register 0x2A for PLLA and Register 0x30 and Register 0x31 for PLLB. The M integer is 16 bits wide. The upper eight bits are stored in Register 0x29 and Register 0x30, and the lower eight bits are stored in Register 0x2A and Register 0x31. The default value is 0x00FD: M = 253. [31:16] PLLx_N_HI[7:0], PLLx_N_LO[7:0] Numerator of the fractional APLL: a 16-bit binary number. The N value can be set using Register 0x2B and Register 0x2C for PLLA and Register 0x32 and Register 0x33 for PLLB. The upper eight bits are stored in Register 0x2B and Register 0x32, and the lower eight bits are stored in Register 0x2C and Register 0x33. The default value is 0: N = 0. [15] Reserved Reserved. [14:11] PLLx_R[3:0] Integer part of APLL: four bits. Only values of 2 to 8 are valid. The four bits are stored in Register 0x2D for PLLA (Bits[6:3]) and Register 0x34 for PLLB (Bits[6:3]). 0010 R = 2 (default). 0011 R = 3. 0100 R = 4. 0101 R = 5. 0110 R = 6. 0111 R = 7. 1000 R = 8. [10:9] PLLx_X[1:0] APLL input clock divider. The two bits are stored in Register 0x2D for PLLA (Bits[2:1]) and Register 0x34 for PLLB (Bits[2:1]). 00 X = 1 (default). 01 X = 2. 10 X = 3. 11 X = 4. 8 PLLx_TYPE APLL operation mode. This bit is stored in Register 0x2D for PLLA (Bit 0) and Register 0x34 for PLLB (Bit 0). 0 Integer mode (default). 1 Fractional mode. [7:4] Reserved Reserved. |
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