ADAU1373BCBZ-R7 datasheet(50/296 Pages) AD

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ADAU1373

Rev. 0 | Page 50 of 296

PLL Mode

If using the PLL, set the dividers so that fPLL is within the range

of 45.158 MHz (1024 kHz × 44.1 kHz) to 49.152 MHz (1024 kHz ×

48 kHz).

fPLL = 256 × fS × (J + 1) × (K + 1)

Example 1—Using a PLL Sample Rate of 48 kHz

For a 48 kHz sample rate (fS), select the J and K such that fPLL is

within the range of 45 MHz to 50 MHz.

fPLL = 256 × D × 48,000

where D = (J + 1) × (K + 1).

For D = 3, fPLL = 36.864 MHz; for D = 4, fPLL = 49.152 MHz;

and for D = 5, fPLL = 61.44 MHz. Setting D = 4 ensures that fPLL

is within the PLL range of 45 MHz to 50 MHz.

To determine the divider values, there are two options, as follows:

•

By setting J = K = 1, then D = 4 because D = (J + 1) × (K + 1).

•

By setting J = 0, K = 3 also results in D = (J + 1) × (K + 1) = 4.

Example 2—Using a PLL Sample Rate of 44.1 kHz

For a 44.1 kHz sample rate (fS), select the J and K such that fPLL is

within the range of 45 MHz to 50 MHz.

fPLL = 256 × D × 44,100

where D = (J + 1) × (K + 1).

For D = 3, fPLL = 33.868 MHz; for D = 4, fPLL = 45.158 MHz; and

for D = 5, fPLL = 56.448 MHz. Setting D = 4 ensures that fPLL is

within the PLL range of 45 MHz to 50 MHz.

To determine the divider values, there are two options, as follows:

•

By setting J = K = 1, then D = 4 because X = (J + 1) × (K + 1).

•

By setting J = 0, K = 3 also results in D = (J + 1) × (K + 1) = 4.

Example 3—Using a PLL Sample Rate of 32 kHz

For a 32 kHz sample rate (fS), select the J and K such that fPLL is

within the range of 45 MHz to 50 MHz.

fPLL = 256 × D × 32,000

where D = (J + 1) × (K + 1).

For D =5, fPLL = 40.96 MHz; for D = 6, fPLL = 49.152 MHz; and

for D = 7, fPLL = 57.344 MHz. Setting D = 6 ensures that fPLL is

within the PLL range of 45 MHz to 50 MHz.

To determine the divider values, there are two options, as follows:

•

Setting J = 1 and K = 2 can result in D = 6.

•

Setting J = 0 and K = 5 also results in D = 6.

Step 3—Calculate APLL multiplier/dividers (X, R, N, M)

If using the analog PLL only, then fIN ≥ 8 MHz.

Next, using the fPLL calculated in Step 2, calculate the PLL X, R,

N, and M values.

For integer mode, use the following:

fPLL = (R/X) × fIN

N and M are ignored.

For fractional mode, use the following:

fPLL = fIN × (R + (N/M))/X

Select the values of R and X for integer mode or R, X, N, and M

for fractional mode.

If the available clock in the system (fIN) is known, and using the

PLL output frequency (fPLL) from Step 2, the values required for

X, R, N, and M for fractional mode or X and R for integer mode

can be calculated using the following equation:

(R/X) = fIN/fPLL (integer mode)

(R + N/M)/X = fIN/fPLL (fractional mode)

Wide selections are possible; refer to Table 11, Table 12, and

Table 13 for popular choices.

Step 4—Master Clock Output

The internal core clock, fCORE, can be made available at the

GPIO1/GPIO2/GPIO3/GPIO4 pins by setting Register 0xE3

or Register 0xE4. The master clock output frequency can

be set using the 5-bit divider (Register 0x41 for PLLA and

used to set the PLL, and Table 18 provides descriptions of the

48 bits that are used for PLL control.

ADAU1373BCBZ-R7 Datasheet(PDF) 50 Page - Analog Devices

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