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ADAU1373BCBZ-R7 Datasheet(PDF) 217 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 217 Page - Analog Devices |
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217 / 296 page  ADAU1373 Rev. 0 | Page 217 of 296 DRC2_CTRL14 REGISTER Address: 0x9D, Reset: 0x20, Name: DRC2_CTRL14 DRC2 Enable Control Table 180. Bit Descriptions for DRC2_CTRL14 Bits Bit Name Settings Description Reset Access 7 DRCNGTGT DRC2 Noise Gate Recovery Target. 0x0 RW 0 Target: DRC minimum output 1 Target: determined by DRC curve 6 DRCNGHDEN DRC2 Noise Gate Recovery Hold Enable. 0x0 RW 0 DRC noise gate recovery hold time disable 1 DRC noise gate recovery hold time enable 5 DRCNGSRC DRC2 Noise Gate Recovery Source. 0x1 RW 0 RMS 1 Peak (default) 4 DRCCESRC DRC2 Compressor/Expander Source. 0x0 RW 0 RMS 1 Peak 3 DRCLMSRC DRC2 Limiter Source. 0x0 RW 0 RMS 1 Peak 2 DRCNGEN DRC2 Noise Gating Enable. 0x0 RW 0 DRC noise gate disable 1 DRC noise gate enable [1:0] DRCEN DRC2 Enable. 0x0 RW 00 None (default) 01 Right channel enable 10 Left channel enable 11 Both channels enable |
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