ADAU1373BCBZ-R7 datasheet(251/296 Pages) AD

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ADAU1373

Rev. 0 | Page 251 of 296

ALC_CTRL6 REGISTER

Address: 0xC8, Reset: 0x00, Name: ALC_CTRL6

ALC Control Register

Table 223. Bit Descriptions for ALC_CTRL6

Bits

Bit Name

Settings

Description

Reset

Access

HLDRST

Recovery Hold Time Counter Clear Control. Noise gate reset hold time setting.

The noise gate is not reset for the hold time set in Register 0xC6.

0x0

Hold time reset after noise gate

Hold time no reset after noise gate

ALCHPF

ALC Embedded High-Pass Filter Enable. ALC high-pass filter enable/disable

setting. The high-pass filter is fixed at 3.7 Hz at a 48 kHz sample rate.

0x0

High-pass filter enable

High-pass filter disable

[5:4]

NGMODE

ALC Noise Gate Mode. ALC noise gate mode selection: Noise Gate Mode 1,

Noise Gate Mode 2, Noise Gate Mode 3, or disable noise gate.

0x0

No noise gate

Noise Gate Mode 1; keeps the gain before ALC enters noise gate

Noise Gate Mode 2; sets the PGA gain to 0 dB

Noise Gate Mode 3; mutes the ALC output to −120 dB

[3:2]

ALCEN

ALC Enable Control. ALC enable/disable control.

0x0

Both channels disabled

Right channel enabled

Left channel enabled

Both channels enabled

[1:0]

ALCMODE

ALC Operation Mode Control. ALC can be applied to digital/analog PGA or

both by setting this register.

0x0

Control digital PGA

Control analog PGA

Control both analog/digital PGA

No use

ADAU1373BCBZ-R7 Datasheet(PDF) 251 Page - Analog Devices

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