MB96F348CWCPMC-GSE2 datasheet(79/109 Pages) CYPRESS

79 / 109 page

MB96340 Series

Document Number: 002-04579 Rev. *A

Page 79 of 109

Valid address

 Valid data

input

tAVDV

A[23:16],

AD[15:0]

EACL:ACE=0

-3tCYC  60

w/o cycle

extension

EACL:ACE=1

-4tCYC  60

tADVDV

AD[15:0]

EACL:ACE=0

-5tCYC/2  60

w/o cycle

extension

EACL:ACE=1

-7tCYC/2  60

RDX pulse width

tRLRH

RDX

3tCYC/2  8-

w/o cycle

extension

RDX

  Valid data input

tRLDV

RDX, AD[15:0]

3tCYC/2  55

w/o cycle

extension

RDX

  Data hold time

tRHDX

RDX, AD[15:0]

Address valid

 Data hold time

tAXDX

A[23:16]

RDX

  ALE  time

tRHLH

RDX, ALE

EACL:STS=1 and

EACL:ACE=1

3tCYC/2  15

other ECL:STS, EA-

CL:ACE setting

tCYC/2  15

Valid address

 ECLK  time

tAVCH

A[23:16], ECLK

tCYC  20

tADVCH

AD[15:0], ECLK

tCYC/2  20

RDX

  ECLK  time

tRLCH

RDX, ECLK

tCYC/2  15

ALE

  RDX  time

tLLRL

ALE, RDX

EACL:STS=0

tCYC/2  15

EACL:STS=1

 15

ECLK

  Valid data input

tCHDV

AD[15:0], ECLK

tCYC  55

(TA  40°C to 125°C, VCC  3.0 to 4.5V, VSS  0.0 V, IOdrive = 5mA, CL = 50pF)

Parameter

Symbol

Conditions

Value

Unit Remarks

Min

Max

MB96F348CWCPMC-GSE2 Datasheet(PDF) 79 Page - Cypress Semiconductor

MB96F348CWCPMC-GSE2 Datasheet(HTML) 79 Page - Cypress Semiconductor

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