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ADAU1373BCBZ-R7 Datasheet(PDF) 156 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 156 Page - Analog Devices |
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156 / 296 page ![]() ADAU1373 Rev. 0 | Page 156 of 296 BCLKDIVA REGISTER Address: 0x47, Reset: 0x00, Name: BCLKDIVA Digital Audio Interface A Settings 2 Table 100. Bit Descriptions for BCLKDIVA Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved. 0x0 RW 5 DAIA_SOURCE Source Clock of the Digital Audio Interface A in Master Mode. Master clock source for Interface A can be set to either PLLA or PLLB. 0x0 RW 0 From PLLA 1 From PLLB [4:2] DAIA_SR Sample Rate of Digital Audio Interface A. Sample rate for Interface A can be set to 32 kHz/24 kHz/16 kHz/12 kHz/8 kHz/8.0182 kHz. 0x0 RW 000 fS (48 kHz) 001 2/3 fS (32 kHz) 010 1/2 fS (24 kHz) 011 1/3 fS (16 kHz) 100 1/4 fS (12 kHz) 101 1/6 fS (8 kHz) 110 2/11 fS (44.1K based, 8.0182 kHz) 111 fS [1:0] BPFA Number of Bit Clocks per Frame of Digital Audio Interface A. Number of bit clocks per frame can be set to 32/64/128/256. 0x0 RW 00 256 01 128 10 64 11 32 |
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