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ADAU1373BCBZ-R7 Datasheet(PDF) 140 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 140 Page - Analog Devices |
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140 / 296 page  ADAU1373 Rev. 0 | Page 140 of 296 PLLB_CTRL4 REGISTER Address: 0x33, Reset: 0x00, Name: PLLB_CTRL4 Numerator (N) of the Fractional PLLB Lower Byte Table 85. Bit Descriptions for PLLB_CTRL4 Bits Bit Name Settings Description Reset Access [7:0] PLLB_N_LO Numerator of the Fractional PLLB LSB. PLLB Fractional Mode Numerator N lower byte. 0x00 RW PLLB_CTRL5 REGISTER Address: 0x34, Reset: 0x00, Name: PLLB_CTRL5 PLLB Type, X and R Value Setting Table 86. Bit Descriptions for PLLB_CTRL5 Bits Bit Name Settings Description Reset Access 7 RESERVED 0x0 RW [6:3] PLLB_R Integer Part of PLLB. Integer (R) of PLLB. 0x0 RW 0010 R = 2 0011 R = 3 0100 R = 4 0101 R = 5 0110 R = 6 0111 R = 7 1000 R = 8 [2:1] PLLB_X PLLB Input Clock Divider. PLLB input clock divider (X). 0x0 RW 00 X = 1 01 X = 2 10 X = 3 11 X = 4 0 PLLB_TYPE PLLB Operation Mode. PLLB mode (fractional or integer). 0x0 RW 0 Integer 1 Fractional |
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