ADAU1373BCBZ-R7 datasheet(138/296 Pages) AD

138 / 296 page

ADAU1373

Rev. 0 | Page 138 of 296

Bits

Bit Name

Settings

Description

Reset

Access

[3:0]

DPLLB_NDIV

DPLLB Clock Divider Setting. DPLLB source selection can be set to one of

the following: Digital Audio Interface A/B/C bit clock/frame clock or

GPIO1/2/3/4 or Master Clock Input 1/2.

0x0

0000

DPLLB output clock frequency: DPLLB input

0001

DPLLB output clock frequency: DPLLB input clock frequency × 1024

0010

DPLLB output clock frequency: DPLLB input clock frequency × 512

0011

DPLLB output clock frequency: DPLLB input clock frequency × 256

0100

DPLLB output clock frequency: DPLLB input clock frequency × 128

0101

DPLLB output clock frequency: DPLLB input clock frequency × 64

0110

DPLLB output clock frequency: DPLLB input clock frequency × 32

0111

DPLLB output clock frequency: DPLLB input clock frequency × 16

1000

DPLLB output clock frequency: DPLLB input clock frequency × 8

1001

DPLLB output clock frequency: DPLLB input clock frequency × 4

1010

DPLLB output clock frequency: DPLLB input clock frequency × 2

1011

Reserved

1100

Reserved

1101

Reserved

1110

Reserved

1111

Reserved

ADAU1373BCBZ-R7 Datasheet(PDF) 138 Page - Analog Devices

ADAU1373BCBZ-R7 Datasheet(HTML) 138 Page - Analog Devices

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