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ADAU1373BCBZ-R7 Datasheet(PDF) 135 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 135 Page - Analog Devices |
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135 / 296 page ![]() ADAU1373 Rev. 0 | Page 135 of 296 PLLA_CTRL5 REGISTER Address: 0x2D, Reset: 0x00, Name: PLLA_CTRL5 PLLA Type, X and R Value Setting Table 79. Bit Descriptions for PLLA_CTRL5 Bits Bit Name Settings Description Reset Access 7 RESERVED Reserved. 0x0 RW [6:3] PLLA_R Integer Part of PLLA. Integer (R) of PLLA. 0x0 RW 0010 R = 2 0011 R = 3 0100 R = 4 0101 R = 5 0110 R = 6 0111 R = 7 1000 R = 8 [2:1] PLLA_X PLLA Input Clock Divider. PLLA input clock divider (X). 0x0 RW 00 X = 1 01 X = 2 10 X = 3 11 X = 4 0 PLLA_TYPE PLLA Operation Mode. PLLA mode (fractional or integer). 0x0 RW 0 Integer 1 Fractional |
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