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ADAU1373BCBZ-R7 Datasheet(PDF) 133 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 133 Page - Analog Devices |
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133 / 296 page  ADAU1373 Rev. 0 | Page 133 of 296 Bits Bit Name Settings Description Reset Access [3:0] DPLLA_NDIV DPLLA Clock Divider Setting. DPLLA clock divider settings from 1 to 1024 in 16 steps. 0x0 RW 0000 DPLLA output clock frequency: DPLLA input 0001 DPLLA output clock frequency: DPLLA input clock frequency × 1024 0010 DPLLA output clock frequency: DPLLA input clock frequency × 512 0011 DPLLA output clock frequency: DPLLA input clock frequency × 256 0100 DPLLA output clock frequency: DPLLA input clock frequency × 128 0101 DPLLA output clock frequency: DPLLA input clock frequency × 64 0110 DPLLA output clock frequency: DPLLA input clock frequency × 32 0111 DPLLA output clock frequency: DPLLA input clock frequency × 16 1000 DPLLA output clock frequency: DPLLA input clock frequency × 8 1001 DPLLA output clock frequency: DPLLA input clock frequency × 4 1010 DPLLA output clock frequency: DPLLA input clock frequency × 2 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved 1011 Reserved PLLA_CTRL1 REGISTER Address: 0x29, Reset: 0x00, Name: PLLA_CTRL1 PLLA Fractional Mode Denominator M High Byte Table 75. Bit Descriptions for PLLA_CTRL1 Bits Bit Name Settings Description Reset Access [7:0] PLLA_M_HI Denominator (M) of the Fractional PLLA Upper Byte. PLLA Fractional Mode Denominator M divider setting upper byte. 0x00 RW PLLA_CTRL2 REGISTER Address: 0x2A, Reset: 0x00, Name: PLLA_CTRL2 PLLA Fractional Mode Denominator M Lower Byte Table 76. Bit Descriptions for PLLA_CTRL2 Bits Bit Name Settings Description Reset Access [7:0] PLLA_M_LO Denominator (M) of the Fractional PLLA Lower Byte. PLLA Fractional Mode Denominator M divider setting lower byte. 0x00 RW |
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