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ADAU1373BCBZ-R7 Datasheet(PDF) 130 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 130 Page - Analog Devices |
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130 / 296 page ![]() ADAU1373 Rev. 0 | Page 130 of 296 PWDN_CTRL2 REGISTER Address: 0x26, Reset: 0x00, Name: PWDN_CTRL2 Power-Down Block Control 2 Table 72. Bit Descriptions for PWDN_CTRL2 Bits Bit Name Settings Description Reset Access 7 LDAC2PDB Left Channel DAC 2 Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 6 RADC2PDB Right Channel DAC 2 Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 5 LDAC1PDB Left Channel DAC1 Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 4 RDAC1PDB Right Channel DAC1 Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 3 LLN2PDB Lineout2 Left Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 2 RLN2PDB Lineout2 Right Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 1 LLN1PDB Lineout1 Left Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up 0 RLN1PDB Lineout1 Right Power-Down Control. 0x0 RW 0 Power down (default) 1 Power up |
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