ADAU1373BCBZ-R7 datasheet(132/296 Pages) AD

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ADAU1373

Rev. 0 | Page 132 of 296

DPLLA_CTRL REGISTER

Address: 0x28, Reset: 0x00, Name: DPLLA_CTRL

DPLLA Control

Table 74. Bit Descriptions for DPLLA_CTRL

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

DPLLA_REF_SEL

DPLLA Source Select. DPLLA source selection can be set to one of the

following: Digital Audio Interface A/B/C bit clock/frame clock or

GPIO1/2/3/4 or Master Clock Input 1/2.

0x0

0000

MCLK1

0001

DPLLA reference clock input: Digital Audio Interface A bit clock

0010

DPLLA reference clock input: Digital Audio Interface B bit clock

0011

DPLLA reference clock input: Digital Audio Interface C bit clock

0100

DPLLA reference clock input: Digital Audio Interface A frame clock

0101

DPLLA reference clock input: Digital Audio Interface B frame clock

0110

DPLLA reference clock input: Digital Audio Interface C frame clock

0111

DPLLA reference clock input: GPIO1

1000

DPLLA reference clock input: GPIO2

1001

DPLLA reference clock input: GPIO3

1010

DPLLA reference clock input: GPIO4

1011

MCLK2

1110

Reserved

1111

Reserved

1101

Reserved

1100

Reserved

ADAU1373BCBZ-R7 Datasheet(PDF) 132 Page - Analog Devices

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