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ADAU1373BCBZ-R7 Datasheet(PDF) 137 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 137 Page - Analog Devices |
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137 / 296 page  ADAU1373 Rev. 0 | Page 137 of 296 DPLLB_CTRL REGISTER Address: 0x2F, Reset: 0x00, Name: DPLLB_CTRL DPLLB Control Table 81. Bit Descriptions for DPLLB_CTRL Bits Bit Name Settings Description Reset Access [7:4] DPLLB_REF_SEL DPLLB Source Select. DPLLB clock divider settings from 1 to 1024 in 16 steps. 0x0 RW 0000 MCLK1 0001 Audio Interface A bit clock 0010 Audio Interface B bit clock 0011 Audio Interface C bit clock 0100 Audio Interface A Frame Clock 0101 Audio Interface B Frame Clock 0110 Audio Interface C Frame Clock 0111 GPIO1 1000 GPIO2 1001 GPIO3 1010 GPIO4 1011 MCLK2 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved |
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