 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADAU1373BCBZ-R7 Datasheet(PDF) 204 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADAU1373BCBZ-R7 Datasheet(HTML) 204 Page - Analog Devices |
|
|
204 / 296 page  ADAU1373 Rev. 0 | Page 204 of 296 DRC1_CTRL14 REGISTER Address: 0x8D, Reset: 0x20, Name: DRC1_CTRL14 DRC1 Enable Control Table 164. Bit Descriptions for DRC1_CTRL14 Bits Bit Name Settings Description Reset Access 7 DRCNGTGT DRC1 Noise Gate Recovery Target. 0x0 RW 0 Target: DRC minimum output 1 Target: determined by DRC curve 6 DRCNGHDEN DRC1 Noise Gate Recovery Hold Enable. 0x0 RW 0 DRC noise gate recovery hold time disable 1 DRC noise gate recovery hold time enable 5 DRCNGSRC DRC1 Noise Gate Recovery Source. 0x1 RW 0 RMS 1 Peak (default) 4 DRCCESRC DRC1 Compressor/Expander Source. 0x0 RW 0 RMS 1 Peak 3 DRCLMSRC DRC1 Limiter Source. 0x0 RW 0 RMS 1 Peak 2 DRCNGEN DRC1 Noise Gating Enable. 0x0 RW 0 DRC noise gate disable 1 DRC noise gate enable [1:0] DRCEN DRC1 Enable. 0x0 RW 00 None (default) 01 Right channel enable 10 Left channel enable 11 Both channels enable |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
