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ADAU1373BCBZ-R7 Datasheet(PDF) 207 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 207 Page - Analog Devices |
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207 / 296 page ![]() ADAU1373 Rev. 0 | Page 207 of 296 DRC2_CTRL1 REGISTER Address: 0x90, Reset: 0x78, Name: DRC2_CTRL1 DRC2 Level Detector Averaging Time and DRC Noise Gate Recovery Time Setting Table 167. Bit Descriptions for DRC2_CTRL1 Bits Bit Name Settings Description Reset Access [7:4] DRCNGREC DRC2 Noise Gate Recovery Time. 0x7 RW 0000 46.875 μs 0001 93.75 μs 0010 187.5 μs 0011 375 μs 0100 750 μs 0101 1.5 ms 0110 3 ms 0111 6 ms (default) 1000 12 ms 1001 24 ms 1010 48 ms 1011 96 ms 1100 192 ms 1101 384 ms 1110 768 ms 1111 1.536 sec [3:0] DRCLELTAV DRC2 RMS Detector Average Time. 0x8 RW 0000 750 μs 0001 1.5 ms 0010 3 ms 0011 6 ms 0100 12 ms 0101 24 ms 0110 48 ms 0111 96 ms 1000 192 ms (default) 1001 384 ms 1010 768 ms |
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