ADAU1373BCBZ-R7 datasheet(147/296 Pages) AD

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ADAU1373

Rev. 0 | Page 147 of 296

CLK1_SOURCE_DIV REGISTER

Address: 0x40, Reset: 0x00, Name: CLK1_SOURCE_DIV

Clock 1 Divide and Core Clock Enable Control

Table 93. Bit Descriptions for CLK1_SOURCE_DIV

Bits

Bit Name

Settings

Description

Reset

Access

COREN

Core Clock Enable. Core clock enable or disable control.

0x0

Core clock disable (default)

Core clock enable

CLK1S_SEL

PLLA Bypass Signal. Clock source selection. Clock source can be set to

either PLLA output or external input.

0x0

Use PLLA clock as Source Clock 1 (default)

Use external clock as Source Clock 1

[5:3]

CLK1SDIV

Source Clock 1 Divider. Source Clock 1 divider settings, 0 through 7 in

eight steps.

0x0

000

Source Clock Divider K = 0

001

Source Clock Divider K = 1

010

Source Clock Divider K = 2

011

Source Clock Divider K = 3

100

Source Clock Divider K = 4

101

Source Clock Divider K = 5

110

Source Clock Divider K = 6

111

Source Clock Divider K = 7

[2:0]

MCLK1DIV

Master Clock 1 Divider. Master Clock 1 divider settings, 0 through 7 in

eight steps.

0x0

000

Divider J = 0

001

Divider J = 1

010

Divider J = 2

011

Divider J = 3

100

Divider J = 4

101

Divider J = 5

110

Divider J = 6

111

Divider J = 7

ADAU1373BCBZ-R7 Datasheet(PDF) 147 Page - Analog Devices

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