ADAU1373BCBZ-R7 datasheet(150/296 Pages) AD

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ADAU1373

Rev. 0 | Page 150 of 296

CLK2_SOURCE_DIV REGISTER

Address: 0x42, Reset: 0x00, Name: CLK2_SOURCE_DIV

Clock 2 Divide and Core Clock Enable Control

Table 95. Bit Descriptions for CLK2_SOURCE_DIV

Bits

Bit Name

Settings

Description

Reset

Access

CLK2EN

Clock 2 Enable. Core clock enable or disable control.

0x0

Clock 2 disable (default)

Clock 2 enable

CLK2S_SEL

PLLB Bypass Signal. Clock source selection. Clock source can be set to

either PLLB output or external input.

0x0

Use PLLB clock as Source Clock 2 (default)

Use external clock as Source Clock 2

[5:3]

CLK2SDIV

Source Clock 2 Divider. Source Clock 2 divider settings, 0 through 7 in

eight steps.

0x0

000

Source Clock Divider K = 0

001

Source Clock Divider K = 1

010

Source Clock Divider K = 2

011

Source Clock Divider K = 3

100

Source Clock Divider K = 4

101

Source Clock Divider K = 5

110

Source Clock Divider K = 6

111

Source Clock Divider K = 7

[2:0]

MCLK2DIV

Master Clock 2 Divider. Master Clock 2 divider settings, 0 through 7 in

eight steps.

0x0

000

Divider J = 0

001

Divider J = 1

010

Divider J = 2

011

Divider J = 3

100

Divider J = 4

101

Divider J = 5

110

Divider J = 6

111

Divider J = 7

ADAU1373BCBZ-R7 Datasheet(PDF) 150 Page - Analog Devices

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