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ADAU1373BCBZ-R7 Datasheet(PDF) 148 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 148 Page - Analog Devices |
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148 / 296 page  ADAU1373 Rev. 0 | Page 148 of 296 CLK1_OUTPUT_DIV REGISTER Address: 0x41, Reset: 0x00, Name: CLK1_OUTPUT_DIV Master Clock 1 Output Divider Control for PLLA Table 94. Bit Descriptions for CLK1_OUTPUT_DIV Bits Bit Name Settings Description Reset Access [7:6] RESERVED Reserved. 0x0 RW 5 CLK1OEN CLK1 Output Enable. Output clock enable control. 0x0 RW 0 CLK1 output disable (default) 1 CLK1 output enable [4:0] CLK1ODIV Output Clock 1 Divider. Output clock divider, settings 0 through 31. 0x00 RW 00000 Output Clock Divider P = 0 00001 Output Clock Divider P = 1 00010 Output Clock Divider P = 2 00011 Output Clock Divider P = 3 00100 Output Clock Divider P = 4 00101 Output Clock Divider P = 5 00110 Output Clock Divider P = 6 00111 Output Clock Divider P = 7 01000 Output Clock Divider P = 8 01001 Output Clock Divider P = 9 01010 Output Clock Divider P = 10 |
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