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ADAU1373BCBZ-R7 Datasheet(PDF) 231 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 231 Page - Analog Devices |
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231 / 296 page  ADAU1373 Rev. 0 | Page 231 of 296 DRC3_CTRL15 REGISTER Address: 0xAE, Reset: 0x00, Name: DRC3_CTRL15 DRC3 Peak to RMS Ratio and RMS Detector Setting Register Table 197. Bit Descriptions for DRC3_CTRL15 Bits Bit Name Settings Description Reset Access 7 RESERVED Reserved. 0x0 RW [6:2] SIG_DET_RMS DRC3 IRQ RMS Value. DRC rms detector setting. 0x00 RW 00000 −30 dB 00001 −31.5 dB 00010 −33 dB xxxxx −1.5 dB step size 11111 −76.5 dB [1:0] SIG_DET_PK DRC3 IRQ Source Ratio Between Peak and RMS. DRC peak to rms ratio setting. 0x0 RW 00 12 dB 01 18 dB 10 24 dB 11 30 dB |
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