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ADAU1373BCBZ-R7 Datasheet(PDF) 232 Page - Analog Devices |
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ADAU1373BCBZ-R7 Datasheet(HTML) 232 Page - Analog Devices |
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232 / 296 page ![]() ADAU1373 Rev. 0 | Page 232 of 296 DRC3_CTRL16 REGISTER Address: 0xAF, Reset: 0x00, Name: DRC3_CTRL16 DRC3 IRQ Enable/Disable and IRQ Source Selection Setting Register Table 198. Bit Descriptions for DRC3_CTRL16 Bits Bit Name Settings Description Reset Access [7:3] RESERVED Reserved. 0x00 RW 2 ALG_NGEN Analog Noise Gate Enable. 0x0 RW 0 Analog noise gate disable 1 Analog noise gate enable 1 DRCIRQ_MODE DRC IRQ Mode. DRC IRQ source selection setting. 0x0 RW 0 DRC IRQ source: rms 1 DRC IRQ source: Peak to rms ratio 0 DRCIRQ_EN DRC IRQ Enable Control. DRC IRQ enable/disable control. 0x0 RW 0 DRC IRQ disable 1 DRC IRQ enable |
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