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ADSP-SC596 Datasheet(PDF) 31 Page - Analog Devices |
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ADSP-SC596 Datasheet(HTML) 31 Page - Analog Devices |
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31 / 134 page  ADSP-SC595/SC596/SC598 Preliminary Technical Data Rev. PrD | Page 31 of 134 | May 2022 DMC0_A05 DMC0 Address 5 Not Muxed DMC0_A05 DMC0_A06 DMC0 Address 6 Not Muxed DMC0_A06 DMC0_A07 DMC0 Address 7 Not Muxed DMC0_A07 DMC0_A08 DMC0 Address 8 Not Muxed DMC0_A08 DMC0_A09 DMC0 Address 9 Not Muxed DMC0_A09 DMC0_A10 DMC0 Address 10 Not Muxed DMC0_A10 DMC0_A11 DMC0 Address 11 Not Muxed DMC0_A11 DMC0_A12 DMC0 Address 12 Not Muxed DMC0_A12 DMC0_A13 DMC0 Address 13 Not Muxed DMC0_A13 DMC0_A14 DMC0 Address 14 Not Muxed DMC0_A14 DMC0_A15 DMC0 Address 15 Not Muxed DMC0_A15 DMC0_BA0 DMC0 Bank Address Input 0 Not Muxed DMC0_BA0 DMC0_BA1 DMC0 Bank Address Input 1 Not Muxed DMC0_BA1 DMC0_BA2 DMC0 Bank Address Input 2 Not Muxed DMC0_BA2 DMC0_CAS DMC0 Column Address Strobe Not Muxed DMC0_CAS DMC0_CK DMC0 Clock Not Muxed DMC0_CK DMC0_CK DMC0 Clock (Complement) Not Muxed DMC0_CK DMC0_CKE DMC0 Clock Enable Not Muxed DMC0_CKE DMC0_CS0 DMC0 Chip Select 0 Not Muxed DMC0_CS0 DMC0_DQ00 DMC0 Data 0 Not Muxed DMC0_DQ00 DMC0_DQ01 DMC0 Data 1 Not Muxed DMC0_DQ01 DMC0_DQ02 DMC0 Data 2 Not Muxed DMC0_DQ02 DMC0_DQ03 DMC0 Data 3 Not Muxed DMC0_DQ03 DMC0_DQ04 DMC0 Data 4 Not Muxed DMC0_DQ04 DMC0_DQ05 DMC0 Data 5 Not Muxed DMC0_DQ05 DMC0_DQ06 DMC0 Data 6 Not Muxed DMC0_DQ06 DMC0_DQ07 DMC0 Data 7 Not Muxed DMC0_DQ07 DMC0_DQ08 DMC0 Data 8 Not Muxed DMC0_DQ08 DMC0_DQ09 DMC0 Data 9 Not Muxed DMC0_DQ09 DMC0_DQ10 DMC0 Data 10 Not Muxed DMC0_DQ10 DMC0_DQ11 DMC0 Data 11 Not Muxed DMC0_DQ11 DMC0_DQ12 DMC0 Data 12 Not Muxed DMC0_DQ12 DMC0_DQ13 DMC0 Data 13 Not Muxed DMC0_DQ13 DMC0_DQ14 DMC0 Data 14 Not Muxed DMC0_DQ14 DMC0_DQ15 DMC0 Data 15 Not Muxed DMC0_DQ15 DMC0_LDM DMC0 Data Mask for Lower Byte Not Muxed DMC0_LDM DMC0_LDQS DMC0 Data Strobe for Lower Byte Not Muxed DMC0_LDQS DMC0_LDQS DMC0 Data Strobe for Lower Byte (Complement) Not Muxed DMC0_LDQS DMC0_ODT DMC0 On-Die Termination Not Muxed DMC0_ODT DMC0_RAS DMC0 Row Address Strobe Not Muxed DMC0_RAS DMC0_RESET DMC0 Reset Not Muxed DMC0_RESET DMC0_RZQ DMC0 External Calibration Resistor Connection Not Muxed DMC0_RZQ DMC0_UDM DMC0 Data Mask for Upper Byte Not Muxed DMC0_UDM DMC0_UDQS DMC0 Data Strobe for Upper Byte Not Muxed DMC0_UDQS DMC0_UDQS DMC0 Data Strobe for Upper Byte (Complement) Not Muxed DMC0_UDQS DMC0_VREF0 DMC0 Voltage Reference Not Muxed DMC0_VREF0 DMC0_WE DMC0 Write Enable Not Muxed DMC0_WE EMSI0_CD EMSI0 Card Detect B PB_15 Table 10. ADSP-SC595/SC596/SC598 400-Ball BGA_ED Signal Descriptions (Continued) Signal Name Description Port Pin Name |
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