ADSP-SC596 datasheet(96/134 Pages) AD

96 / 134 page

Rev. PrD

Page 96 of 134

May 2022

ADSP-SC595/SC596/SC598

Preliminary Technical Data

General-Purpose IO Port Timing

Table 58 and Figure 29 describe I/O timing, related to the general-purpose ports (PORT).

General-Purpose I/O Timer Cycle Timing

Table 59, Table 60, and Figure 30 describe timer expired operations related to the general-purpose timer (TIMER0). The width value is the

timer period assigned in the TMx_TMRn_WIDTH register and can range from 1 to 232 – 1. When externally generated, the TMx_CLK

clock is called fTMRCLKEXT:

Table 58. General-Purpose Port Timing

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirement

tWFI

General-Purpose Port Pin Input Pulse Width

2 × tSCLK0 – 1.5

Figure 29. General-Purpose Port Timing

Table 59. Timer Cycle Timing—Internal Mode

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tWL

Timer Pulse Width Input Low (Measured In SCLK0 Cycles)1

1 The minimum pulse width applies for timer signals in width capture and external clock modes.

2 × tSCLK0

tWH

Timer Pulse Width Input High (Measured In SCLK0 Cycles)1 2 × tSCLK0

Switching Characteristic

tHTO

Timer Pulse Width Output (Measured In SCLK0 Cycles)2

2 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 2 to 232 – 1).

tSCLK0 × WIDTH – 1.7

tSCLK0 × WIDTH + 1.5

Table 60. Timer Cycle Timing—External Mode

All specifications are based on simulation data and are subject to change without notice.

Parameter

Min

Max

Unit

Timing Requirements

tWL

Timer Pulse Width Input Low (Measured In EXT_CLK Cycles)1

1 The minimum pulse width applies for timer signals in width capture and external clock modes.

2 × tEXT_CLK

tWH

Timer Pulse Width Input High (Measured In EXT_CLK Cycles)1 2 × tEXT_CLK

tEXT_CLK

Timer External Clock Period2

2 This specification indicates the minimum instantaneous width or period that can be tolerated due to duty cycle variation or jitter on the external TMR_CLK. For the external

TMR_CLK maximum frequency, see the fTMRCLKEXT specification in Table 22.

tTMRCLKEXT

Switching Characteristic

tHTO

Timer Pulse Width Output (Measured In EXT_CLK Cycles)3

3 WIDTH refers to the value in the TMRx_WIDTH register (it can vary from 1 to 232 – 1).

tEXT_CLK × WIDTH – 1.5

tEXT_CLK × WIDTH + 1.5

GPIO INPUT

tWFI

tTMRCLKEXT

fTMRCLKEXT

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ADSP-SC596 Datasheet(PDF) 96 Page - Analog Devices

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