ADSP-SC596 datasheet(21/134 Pages) AD

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ADSP-SC595/SC596/SC598

Preliminary Technical Data

Rev. PrD

Page 21 of 134

May 2022

actively load data from serial memories. In external host boot

modes, the processors receive data over a serial interface from

an external host device.

The boot modes are shown in Table 7. These modes are imple-

mented by the SYS_BMODE[n] bits of the reset configuration

initiated resets.

In the ADSP-SC595/SC596/SC598 processors, the Arm Cortex-

A55 (Core 0) controls the boot process, including loading all

internal and external memory. The option for secure boot is

available on all models.

Thermal Monitoring Unit (TMU)

The thermal monitoring unit (TMU) provides on-chip tem-

perature measurement for applications that require substantial

power consumption. The TMU is integrated into the processor

die and digital infrastructure using an MMR-based system

access to measure the die temperature variations in real-time.

TMU features include the following:

• On-chip temperature sensing

• Programmable over temperature and under temperature

limits

• Programmable conversion rate

• Averaging feature available

Power Supplies

The processors have separate power supply connections for

• Internal (VDD_INT)

• External (VDD_EXT)

• External (VDD_REF)

• HADC/TMU (VDD_ANA)

• DMC (VDD_DMC)

• PLL (VDD_PLL)

All power supplies must meet the specifications provided in the

Preliminary Operating Conditions section. All external supply

pins must be connected to the same power supply.

Power Management

As shown in Table 8, the processors support six different power

domains, which maximizes flexibility while maintaining com-

pliance with industry standards and conventions.

The power dissipated by a processor is largely a function of the

clock frequency and the square of the operating voltage. For

example, reducing the clock frequency by 25% results in a 25%

reduction in dynamic power dissipation.

Power-Up and Power-Down Sequencing

At all times (including during power-up/power-down sequenc-

ing), the VDD_REF, VDD_ANA, and VDD_EXT supplies must

stay within the VDELTA_EXT_REF specification listed in the Pre-

liminary Operating Conditions table. Processor pins in the

VDD_EXT domain might have an unknown state during

power-up/power-down. External components sharing these

pins on the board must determine if there are any issues that

need addressing based on this behavior. See the ADSP-

SC595/SC596/SC598 Designer Quick Reference for pins in the

VDD_EXT domain. SYS_XTAL0 and SYS_XTAL1 oscillations

(SYS_CLKIN0 and SYS_CLKIN1) start when power is applied

to the VDD_REF pins. The rising edge of SYS_HWRST initiates

the PLL locking sequence. The rising edge of SYS_HWRST

must occur after all voltage supplies and SYS_CLKIN0 and

SYS_CLKIN1 oscillations are valid. For further details and

information, see the Power-Up Reset Timing section.

Target Board JTAG Emulator Connector

The Analog Devices DSP tools product line of JTAG emulators

uses the IEEE 1149.1 JTAG test access port of the processors to

monitor and control the target board processor during emula-

tion. The Analog Devices DSP tools product line of JTAG

emulators provides emulation at full processor speed, allowing

inspection and modification of memory, registers, and proces-

sor stacks. The processor JTAG interface ensures the emulator

does not affect target system loading or timing.

For information on JTAG emulator operation, see the appropri-

ate emulator hardware user’s guide at SHARC Processors

Software and Tools.

SYSTEM DEBUG

The processors include various features that allow easy system

debug. These are described in the following sections.

Table 7. Boot Modes

SYS_BMODE[n] Setting

Boot Mode

000

No boot

001

SPI2 flash

010

External SPI2 host

011

External UART0 host

100

External LP0 host

101

Octal SPI flash

110

eMSI boot (eMMC)

Table 8. Power Domains

Power Domain

VDD Range

All Internal Logic

VDD_INT

DDR3/DDR3L

VDD_DMC

HADC/TMU

VDD_ANA

SYS_CLKIN0/1

VDD_REF

1 VDD_REF requires a minimum of 10 nF and 100 nF decoupling capacitance to

meet source/sink requirements.

PLL0/1

VDD_PLL

2 Connect VDD_PLL to VDD_INT. See ADSP-SC595/SC596/SC598 Designer Quick

Reference for additional details.

All Other I/O (Includes SYS, JTAG, and

Ports Pins)

VDD_EXT

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